INSTRUCTION SET
S3C4510B
FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE
15
14
13
12
11
10
8
7
0
Rd
Offset8
0
0
0
Op
[7:0] Immediate Value
[10:8] Source/Destination Register
[12:11] Opcode
0 = MOV
1 = CMP
2 = ADD
3 = SUB
Figure 3-32. Format 3
OPERATIONS
The instructions in this group perform operations between a Lo register and an 8-bit immediate value. The
THUMB assembler syntax is shown in Table 3-10.
NOTE
All instructions in this group set the CPSR condition codes.
Table 3-10. Summary of Format 3 Instructions
OP
00
THUMB Assembler
MOV Rd, #Offset8
CMP Rd, #Offset8
ARM Equivalent
MOVS Rd, #Offset8
CMP Rd, #Offset8
Action
Move 8-bit immediate value into Rd.
01
Compare contents of Rd with 8-bit immediate
value.
10
11
ADD Rd, #Offset8
SUB Rd, #Offset8
ADDS Rd, Rd, #Offset8 Add 8-bit immediate value to contents of Rd and
place the result in Rd.
SUBS Rd, Rd, #Offset8 Subtract 8-bit immediate value from contents of
Rd and place the result in Rd.
INSTRUCTION CYCLE TIMES
All instructions in this format have an equivalent ARM instruction as shown in Table 3-10. The instruction cycle
times for the THUMB instruction are identical to that of the equivalent ARM instruction.
Examples
MOV
CMP
ADD
SUB
R0, #128
R2, #62
R1, #255
R6, #145
; R0 : = 128 and set condition codes
; Set condition codes on R2 - 62
; R1 : = R1 + 255 and set condition codes
; R6 : = R6 - 145 and set condition codes
3-70
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