欢迎访问ic37.com |
会员登录 免费注册
发布采购

K9K1208D0C 参数 Datasheet PDF下载

K9K1208D0C图片预览
型号: K9K1208D0C
PDF下载: 下载PDF文件 查看货源
内容描述: 64M ×8位, 32M x 16位NAND闪存 [64M x 8 Bit , 32M x 16 Bit NAND Flash Memory]
分类和应用: 闪存
文件页数/大小: 39 页 / 955 K
品牌: SAMSUNG [ SAMSUNG ]
 浏览型号K9K1208D0C的Datasheet PDF文件第26页浏览型号K9K1208D0C的Datasheet PDF文件第27页浏览型号K9K1208D0C的Datasheet PDF文件第28页浏览型号K9K1208D0C的Datasheet PDF文件第29页浏览型号K9K1208D0C的Datasheet PDF文件第31页浏览型号K9K1208D0C的Datasheet PDF文件第32页浏览型号K9K1208D0C的Datasheet PDF文件第33页浏览型号K9K1208D0C的Datasheet PDF文件第34页  
K9K1208Q0C  
K9K1208D0C  
K9K1208U0C  
K9K1216Q0C  
K9K1216D0C  
K9K1216U0C  
FLASH MEMORY  
BLOCK ERASE  
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup com-  
mand(60h). Only address A14 to A25 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address  
loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory  
contents are not accidentally erased due to external noise conditions.  
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the  
erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.  
Figure 12. Block Erase Operation  
tBERS  
R/B  
Pass  
60h  
I/O0  
Fail  
I/Ox  
70h  
Address Input(3Cycle)  
Block Add. : A9 ~ A25  
D0h  
READ STATUS  
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether  
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs  
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows  
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE  
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register  
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read  
cycle, a read command(00h or 50h) should be given before serial access cycle.  
Table4. Read Status Register Definition  
I/O #  
Status  
Definition  
"0" : Successful Program / Erase  
I/O 0  
Program / Erase  
"1" : Error in Program / Erase  
I/O 1  
I/O 2  
"0"  
"0"  
"0"  
"0"  
"0"  
Reserved for Future  
Use  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
Device Operation  
Write Protect  
Not use  
"0" : Busy  
"1" : Ready  
"1" : Not Protected  
I/O 7  
"0" : Protected  
Don’t care  
I/O 8~15  
30  
 复制成功!