M366S2953MTS
PC133/PC100 Unbuffered DIMM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200W
50W
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50W
50pF
50pF
870W
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-75
15
20
20
45
-1H
-1L
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
20
20
20
20
50
ns
ns
ns
ns
us
ns
CLK
-
1
1
1
1
20
Row precharge time
Row active time
20
tRAS(min)
tRAS(max)
tRC(min)
50
100
Row cycle time
65
70
70
1
2, 5
5
Last data in to row precharge
Last data in to Active delay
tRDL(min)
tDAL(min)
2
2 CLK + tRP
Last data in to new col. address delay
Last data in to burst stop
tCDL(min)
tBDL(min)
tCCD(min)
1
1
1
2
CLK
CLK
CLK
2
2
3
Col. address to col. address delay
Number of valid output data
CAS latency=3
CAS latency=2
ea
4
-
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
REV. 0.0 Dec. 2001
SAMSUNG [ SAMSUNG ]
