S T U/D421S
S amHop Microelectronics C orp.
Aug.20,2006
P -C hannel Logic Level E nhancement Mode Field E ffect Transistor
P R ODUC T S UMMAR Y
V
DS S
-40V
F E AT UR E S
( m
W
) Max
I
D
-10A
R
DS (ON)
S uper high dense cell design for low R
DS (ON
).
45 @ V
G S
= -10V
60 @ V
G S
= -4.5V
R ugged and reliable.
TO-252 and TO-251 P ackage.
D
D
G
S
G
D
S
G
S TU S E R IE S
TO-252AA(D-P AK)
S TD S E R IE S
TO-251(l-P AK)
S
AB S OL UTE MAXIMUM R ATINGS
P arameter
Drain-S ource Voltage
Gate-S ource Voltage
Drain C urrent-C ontinuous @ Ta
-P ulsed
b
a
(T
A
=25 C unles s otherwis e noted)
S ymbol
V
DS
V
GS
Limit
-40
20
-10
-8.3
-50
-10
50
35
-55 to 175
W
C
Unit
V
V
A
A
A
A
25 C
70 C
I
D
I
DM
I
S
P
D
T
J
, T
S TG
Drain-S ource Diode Forward C urrent
a
Maximum P ower Dissipation
a
Ta= 25 C
Ta=70 C
Operating Junction and S torage
Temperature R ange
THE R MAL C HAR AC TE R IS TIC S
Thermal R esistance, Junction-to-C ase
Thermal R esistance, Junction-to-Ambient
R
JC
R
JA
3
50
C /W
C /W
SAMHOP [ SAMHOP MICROELECTRONICS CORP. ]
