Datasheet
BR24G08-3
WP Valid Timing (Write Cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so on, pay attention to the following WP valid
timing. During write cycle execution, inside cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to take in D0 of
data(in page write cycle, the first byte data) is the cancel invalid area.
WP input in this area becomes Don't care. The area from the rise of SCL to take in D0 to the stop condition input is the
cancel valid area. Furthermore, after the execution of forced end by WP, the IC enters standby status.
・Rise of SDA
・Rise of D0 taken clock
SCL
SCL
SDA
D1
D0 ACK
SDA D0
ACK
Enlarged view
Enlarged view
S
A
A
C
K
L
A
C
K
L
A
C
K
L
S
T
O
P
tWR
T
A
R
T
Slave
Word
SDA
WP
D7 D6 D5
D2 D1 D0
D4 D3
C
K
L
Data
address
address
WP cancel invalid area
WP cancel valid area
Data is not written.
WP cancel invalid area
Figure 42. WP Valid Timing
Command Cancel by Start Condition and Stop Condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Figure
43.) However, within ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and
stop condition cannot be input, so reset is not available. Therefore, execute software reset. When command is cancelled by
start-stop condition during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined. Therefore, it is not possible to carry out current read cycle in succession. To carry out read cycle in succession,
carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Figure 43. Case of Cancel by Start, Stop Condition during Slave Address Input
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