ADSP-BF531/ADSP-BF532/ADSP-BF533
External Port Bus Request and Grant Cycle Timing
Table 26 and Figure 16 describe external port bus request and
bus grant operations.
Table 26. External Port Bus Request and Grant Cycle Timing
VDDEXT = 1.8 V
LQFP/PBGA Packages CSP_BGA Package
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
All Packages
Parameter
Min
Max
Min
Max
Min
Max
Unit
Timing Requirements
tBS BR Asserted to CLKOUT High Setup
tBH CLKOUT High to BR Deasserted Hold Time
Switching Characteristics
4.6
1.0
4.6
1.0
4.6
0.0
ns
ns
tSD CLKOUT Low to AMSx, Address, and ARE/AWE Disable
tSE CLKOUT Low to AMSx, Address, and ARE/AWE Enable
tDBG CLKOUT High to BG High Setup
tEBG CLKOUT High to BG Deasserted Hold Time
tDBH CLKOUT High to BGH High Setup
tEBH CLKOUT High to BGH Deasserted Hold Time
4.5
4.5
6.0
6.0
6.0
6.0
4.5
4.5
5.5
4.6
5.5
4.6
4.5
4.5
3.6
3.6
3.6
3.6
ns
ns
ns
ns
ns
ns
CLKOUT
tBH
tBS
BR
tSD
tSE
AMSx
tSD
tSE
ADDR 19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
tEBH
BGH
Figure 16. External Port Bus Request and Grant Cycle Timing
Rev. H
| Page 32 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
