ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Write Cycle Timing
Table 24. Asynchronous Memory Write Cycle Timing
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSARDY
tHARDY
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
4.0
1.0
4.0
0.0
ns
ns
Switching Characteristics
tDDAT
tENDAT
tDO
DATA15–0 Disable After CLKOUT
6.0
6.0
6.0
6.0
ns
ns
ns
ns
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
1.0
1.0
1.0
0.8
tHO
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
PROGRAMMED ACCESS
WRITE ACCESS EXTEND HOLD
2 CYCLES 1 CYCLE 1 CYCLE
SETUP
2 CYCLES
CLKOUT
AMSx
tDO
tHO
ABE1–0
ADDR19–1
tDO
tHO
AWE
tSARDY tHARDY
ARDY
tHARDY
tSARDY
tENDAT
tDDAT
DATA 15–0
Figure 14. Asynchronous Memory Write Cycle Timing
Rev. H
| Page 30 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
