ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Read Cycle Timing
Table 23. Asynchronous Memory Read Cycle Timing
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
2.1
1.0
4.0
1.0
2.1
0.8
4.0
0.0
ns
ns
ns
ns
tHDAT
tSARDY
tHARDY
Switching Characteristics
tDO
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
6.0
6.0
ns
ns
tHO
1.0
0.8
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, ARE.
SETUP
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
2 CYCLES
CLKOUT
AMSx
tDO
tHO
ABE1–0
ADDR19–1
AOE
ARE
tDO
tHO
tHARDY
tSARDY
tHARDY
ARDY
tSARDY
tSDAT
tHDAT
DATA 15–0
Figure 13. Asynchronous Memory Read Cycle Timing
Rev. H
| Page 29 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
