ADSP-BF531/ADSP-BF532/ADSP-BF533
SDRAM Interface Timing
Table 25. SDRAM Interface Timing1
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSSDAT
tHSDAT
DATA Setup Before CLKOUT
DATA Hold After CLKOUT
2.1
0.8
1.5
0.8
ns
ns
Switching Characteristics
tDCAD
tHCAD
tDSDAT
tENSDAT
tSCLK
Command, ADDR, Data Delay After CLKOUT2
6.0
6.0
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
Command, ADDR, Data Hold After CLKOUT2
Data Disable After CLKOUT
Data Enable After CLKOUT
CLKOUT Period3
1.0
1.0
1.0
1.0
7.5
2.5
2.5
10.0
2.5
tSCLKH
tSCLKL
CLKOUT Width High
CLKOUT Width Low
2.5
1 SDRAM timing for TJ > 105°C is limited to 100 MHz.
2 Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
3 Refer to Table 13 on Page 22 for maximum fSCLK at various VDDINT
.
tSCLK
CLKOUT
tSSDAT
tHSDAT
tSCLKL
tSCLKH
DATA (IN)
tDCAD
tDSDAT
tENSDAT
tHCAD
DATA (OUT)
tDCAD
tHCAD
COMMAND,
ADDRESS
(OUT)
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 15. SDRAM Interface Timing
Rev. H
| Page 31 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
