ADSP-BF531/ADSP-BF532/ADSP-BF533
Parallel Peripheral Interface Timing
Table 27 and Figure 17 through Figure 21 on Page 34 describe
parallel peripheral interface operations.
Table 27. Parallel Peripheral Interface Timing
VDDEXT = 1.8 V
LQFP/PBGA Packages CSP_BGA Package
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
All Packages
Parameter
Min
Max
Min
Max
Min
Max
Unit
Timing Requirements
tPCLKW PPI_CLK Width
tPCLK PPI_CLK Period1
8.0
8.0
6.0
ns
ns
20.0
6.0
20.0
6.0
15.0
4.02
tSFSPE External Frame Sync Setup Before PPI_CLK Edge
(Nonsampling Edge for Rx, Sampling Edge for Tx)
ns
ns
tHFSPE External Frame Sync Hold After PPI_CLK
tSDRPE Receive Data Setup Before PPI_CLK
tHDRPE Receive Data Hold After PPI_CLK
1.02
3.5
1.5
1.02
3.5
1.5
1.02
3.5
1.5
ns
ns
ns
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE Internal Frame Sync Delay After PPI_CLK
tHOFSPE Internal Frame Sync Hold After PPI_CLK
tDDTPE Transmit Data Delay After PPI_CLK
tHDTPE Transmit Data Hold After PPI_CLK
11.0
11.0
8.0
9.0
8.0
9.0
ns
ns
ns
ns
1.7
1.8
1.7
1.8
1.7
1.8
1 PPI_CLK frequency cannot exceed fSCLK/2
2 Applies when PPI_CONTROL Bit 8 is cleared. See Figure 18 on Page 33 and Figure 21 on Page 34.
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_CLK
PPI_FS1/2
PPI_DATA
tDFSPE
tPCLKW
tHOFSPE
tPCLK
tSDRPE
tHDRPE
Figure 17. PPI GP Rx Mode with Internal Frame Sync Timing
DATA SAMPLED /
DATA SAMPLED /
FRAME SYNC SAMPLED
FRAME SYNC SAMPLED
PPI_CLK
tPCLKW
tSFSPE
tHFSPE
tPCLK
PPI_FS1/2
PPI_DATA
tSDRPE
tHDRPE
Figure 18. PPI GP Rx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 1)
Rev. H
| Page 33 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
