ADSP-BF531/ADSP-BF532/ADSP-BF533
TIMING SPECIFICATIONS
Clock and Reset Timing
Table 21 and Figure 11 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 26, combinations of
CLKIN and clock multipliers/divisors must not result in core/
system clocks exceeding the maximum limits allowed for the
processor, including system clock restrictions related to supply
voltage.
Table 21. Clock and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tCKIN
CLKIN Period1, 2, 3, 4
25.0
100.0
ns
ns
ns
ns
ns
tCKINL
tCKINH
tWRST
tNOBOOT
CLKIN Low Pulse
10.0
CLKIN High Pulse
RESET Asserted Pulse Width Low5
RESET Deassertion to First External Access Delay6
10.0
11 tCKIN
3 tCKIN
5 tCKIN
1 Applies to PLL bypass mode and PLL non bypass mode.
2 CLKIN frequency must not change on the fly.
3 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 11 on Page 22 through
Table 13 on Page 22. Since the default behavior of the PLL is to multiply the CLKIN frequency by 10, the 400 MHz speed grade parts cannot use the full CLKIN period range.
4 If the DF bit in the PLL_CTL register is set, then the maximum tCKIN period is 50 ns.
5 Applies after power-up sequence is complete. See Table 22 and Figure 12 for power-up reset timing.
6 Applies when processor is configured in No Boot Mode (BMODE1-0 = b#00).
tCKIN
CLKIN
tNOBOOT
tCKINL
tCKINH
tWRST
RESET
Figure 11. Clock and Reset Timing
Table 22. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tRST_IN_PWR RESET Deasserted After the VDDINT, VDDEXT, VDDRTC, and CLKIN Pins Are Stable and 3500 tCKIN
ns
Within Specification
tRST_IN_PWR
RESET
CLKIN
V
DD_SUPPLIES
In Figure 12, VDD_SUPPLIES is VDDINT, VDDEXT, VDDRTC
Figure 12. Power-Up Reset Timing
Rev. H
| Page 28 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
