ADSP-BF531/ADSP-BF532/ADSP-BF533
DATA
SAMPLED
FRAME SYNC
SAMPLED
PPI_CLK
tPCLKW
tSFSPE
tHFSPE
tPCLK
PPI_FS1/2
PPI_DATA
tSDRPE
tHDRPE
Figure 19. PPI GP Rx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 0)
FRAME SYNC
DRIVEN
DATA
DRIVEN
tPCLK
DATA
DRIVEN
PPI_CLK
PPI_FS1/2
PPI_DATA
tDFSPE
tPCLKW
tHOFSPE
tDDTPE
tHDTPE
Figure 20. PPI GP Tx Mode with Internal Frame Sync Timing
DATA DRIVEN /
FRAME SYNC SAMPLED
PPI_CLK
PPI_FS1/2
PPI_DATA
tSFSPE
tHFSPE
tPCLKW
tPCLK
tDDTPE
tHDTPE
Figure 21. PPI GP Tx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 1)
FRAME SYNC
SAMPLED
DATA
DRIVEN
PPI_CLK
PPI_FS1/2
PPI_DATA
tSFSPE
tHFSPE
tPCLKW
tPCLK
tDDTPE
tHDTPE
Figure 22. PPI GP Tx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 0)
Rev. H
| Page 34 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
