AD9888
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ACK
SDA
SCL
Figure 24. Serial Interface—Typical Byte Transfer
ACTIVITY
DETECT
SYNC SLICER
SYNC SEPARATOR
INTEGRATOR
1/S
COMP
SYNC
MUX5
NEGATIVE PEAK
CLAMP
SOGIN0
SOGIN1
VSYNC
MUX1
HSYNC0
HSYNC1
SOGOUT
MUX5
PLL
ACTIVITY
DETECT
POLARITY
DETECT
HSYNCOUT
PIXEL CLOCK
CLOCK
GENERATOR
MUX2
COAST
MUX3
POLARITY
DETECT
VSYNC0
VSYNC1
VSYNCOUT
MUX5
ACTIVITY
DETECT
POLARITY
DETECT
MUX4
Figure 25. Sync Processing Block Diagram
The AD9888 can digitize graphics signals over a very wide
range of frequencies (10 MHz to 205 MHz). Often, character-
istics that are beneficial at one frequency can be detrimental at
another. Analog bandwidth is one such characteristic. For UXGA
resolutions (up to 205 MHz), a very high analog bandwidth is
desirable because of the fast input signal slew rates. For VGA
and lower resolutions (down to 12.5 MHz), a very high band-
width is not desirable because it allows excess noise to pass
through. To accommodate these varying needs, the AD9888
includes variable analog bandwidth control. Four settings are
available (75 MHz, 150 MHz, 300 MHz, and 500 MHz),
allowing the analog bandwidth to be matched with the resolu-
tion of the incoming graphics signal.
the opposite side of the PC board from the AD9888, as that
interposes resistive vias in the path.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane => capacitor => power pin. Do not make the power
connection between the capacitor and the power pin. Placing a
via underneath the capacitor pads, down to the power plane, is
generally the best approach.
It is particularly important to maintain low noise and good
stability of PVD (the clock generator supply). Abrupt changes in
PVD can result in similarly abrupt changes in sampling clock
phase and frequency. This can be avoided by careful attention
to regulation, filtering, and bypassing. It is highly desirable to
provide separate regulated supplies for each of the analog cir-
cuitry groups (VD and PVD).
Power Supply Bypassing
It is recommended to bypass each power supply pin with a 0.1 µF
capacitor. The exception is in the case where two or more supply
pins are adjacent to each other. For these groupings of powers/
grounds, it is only necessary to have one bypass capacitor. The
fundamental idea is to have a bypass capacitor within about
0.5 cm of each power pin. Also, avoid placing the capacitor on
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog supply
regulator, which can in turn produce changes in the regulated
–28–
REV. B
ROCHESTER [ Rochester Electronics ]
