AD9888
14
7
Hsync Detect
The sync processing block diagram (Figure 25) shows
where this function is implemented.
This bit is used to indicate when activity is detected on
the selected Hsync input pin. If HSYNC is held high or
low, activity will not be detected.
14
3
AVS – Active Vsync
This bit indicates which Vsync source is being used; the
Vsync input or the output from the sync separator. Bit 4
in this register is what determines which is active. If both
Vsync and SOG are detected, the user can determine which
has priority via Bit 0 in Register 0EH. The user can override
this function via Bit 1 in Register 0EH. If the override bit
is set to Logic 1, this bit will be forced to whatever the
state of Bit 0 in Register 0EH is set to.
Table XXV. Hsync Detection Results
Detect
Function
0
1
No Activity Detected
Activity Detected
The sync processing block diagram shows where this
function is implemented.
Table XXIX. Active Vsync Results
14
6
AHS – Active Hsync
Bit 5 (Vsync Detect)
Override
AVS
This bit indicates which Hsync input source is being used
by the PLL (Hsync input or Sync-on-Green). Bits 7 and 1
in this register are what determine which source is used. If
both Hsync and SOG are detected, the user can determine
which has priority via Bit 3 in register 0EH. The user can
override this function via Bit 4 in Register 0EH. If the
override bit is set to Logic 1, then this bit will be forced
to whatever the state of Bit 3 in Register 0EH is set to.
0
1
X
0
0
1
1
0
Bit 0 in 0EH
AVS = 1 means Sync separator.
AVS = 0 means Vsync input.
The override bit is in register 0Eh, Bit 1.
Table XXVI. Active Hsync Results
14
2 Detected Vsync Output Polarity Status
This bit reports the status of the Vsync output polarity
detection circuit. It can be used to determine the polarity
of the Vsync input. The detection circuit’s location is
shown in the sync processing block diagram (Figure 25).
Bit 7
(Hsync
Detect)
Bit 1
(SOG
Detect)
Bit 4, Reg
OEH
(Override)
AHS
0
0
1
1
X
0
1
0
1
X
0
0
0
0
1
Bit 3 in 0Eh
1
0
Bit 3 in 0Eh
Bit 3 in 0Eh
Table XXX. Detected Vsync Input Polarity Status
Vsync Polarity Status
Result
0
1
Vsync Polarity is Active High.
Vsync Polarity is Active Low.
AHS = 0 means use the HSYNC pin input for HSYNC.
AHS = 1 means use the SOG pin input for HSYNC.
The override bit is in Register 0EH, Bit 4.
14
1
Sync-on-Green Detect
This bit is used to indicate when Sync activity is detected
on the selected Sync-on-Green input pin.
14
5
Detected Hsync Input Polarity Status
This bit reports the status of the HSYNC input polarity
detection circuit. It can be used to determine the polarity
of the HSYNC input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 25).
Table XXXI. Sync-on-Green Detection Results
Detect
Function
0
1
No Activity Detected
Activity Detected
Table XXVII. Detected Hsync Input Polarity Status
The Sync Processing Block Diagram (Figure 25) shows
where this function is implemented.
HSYNC Polarity Status
Result
0
1
Hsync Polarity is Negative.
Hsync Polarity is Positive.
14
0
Detected COAST Polarity Status
This bit reports the status of the coast input polarity
detection circuit. It can be used to determine the polarity
of the COAST input. The detection circuit’s location is
shown in Figure 25.
14
4
Vsync Detect
This bit is used to indicate when activity is detected on
the selected Vsync input pin. If Vsync is held high or low,
activity will not be detected.
Table XXXII. Detected COAST Input Polarity Status
Table XXVIII. Vsync Detection Results
HSYNC Polarity Status
Result
0
1
COAST Polarity is Negative.
COAST Polarity is Positive.
Detect
Function
0
1
No Activity Detected
Activity Detected
–24–
REV. B
ROCHESTER [ Rochester Electronics ]
