AD9888
2-WIRE SERIAL CONTROL PORT
base address autoincrements by one for each byte of data written
after the data byte intended for the base address. If more bytes are
transferred than there are available addresses, the address will not
increment and remain at its maximum value of 19h. Any base
address higher than 19H will not produce an acknowledge signal.
A 2-wire serial control interface is provided. Up to two AD9888
devices may be connected to the 2-wire serial interface, with
each device having a unique address.
The 2-wire serial interface comprises a clock (SCL) and a
bidirectional data (SDA) pin. The AD9888 acts as a slave for
receiving and transmitting data over the serial interface. When
the serial interface is not active, the logic levels on SCL and
SDA are pulled high by external pull-up resistors.
Data are read from the control registers of the AD9888 in a
similar manner. Reading requires two data transfer operations.
The base address must be written with the R/W bit of the slave
address byte Low to set up a sequential read operation.
Data received or transmitted on the SDA line must be stable for
the duration of the positive-going SCL pulse. Data on SDA
must change only when SCL is low. If SDA changes state
while SCL is high, the serial interface interprets that action as a
start or stop sequence.
Reading (the R/W bit of the slave address byte high) begins at
the previously established base address. The address of the read
register autoincrements after each byte is transferred.
To terminate a read/write sequence to the AD9888, a stop
signal must be sent. A stop signal comprises a low-to-high tran-
sition of SDA while SCL is high.
There are five components to serial bus operation:
• Start signal
A repeated start signal occurs when the master device driving the
serial interface generates a start signal without first generating a
stop signal to terminate the current communication. This is used
to change the mode of communication (read, write) between the
slave and master without releasing the serial interface lines.
• Slave address byte
• Base register address byte
• Data byte to read or write
• Stop signal
When the serial interface is inactive (SCL and SDA are high),
communications are initiated by sending a start signal. The start
signal is a high-to-low transition on SDA while SCL is high.
This signal alerts all slaved devices that a data transfer sequence
is coming.
Serial Interface Read/Write Examples
Write to One Control Register
Start Signal
Slave Address Byte (R/W Bit = Low)
Base Address Byte
The first eight bits of data transferred after a start signal comprise
a 7-bit slave address (the first seven bits) and a single R/W bit
(the eighth bit). The R/W bit indicates the direction of data
transfer, read from (1) or write to (0) the slave device . If the
transmitted slave address matches the address of the device
(set by the state of the A0 input pin in Table XLI), the AD9888
acknowledges by bringing SDA low on the ninth SCL pulse. If
the addresses do not match, the AD9888 does not acknowledge
Data Byte to Base Address
Stop Signal
Write to Four Consecutive Control Registers
Start Signal
Slave Address Byte (R/W Bit = Low)
Base Address Byte
Data Byte to Base Address
Data Byte to (Base Address + 1)
Data Byte to (Base Address + 2)
Data Byte to (Base Address + 3)
Stop Signal
Table XLI. Serial Port Addresses
Bit 7
(MSB) Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
A0
Read from One Control Register
Start Signal
Slave Address Byte (R/W Bit = Low)
Base Address Byte
A6
A5
A4
A3
A2
A1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
Start Signal
Slave Address Byte (R/W Bit = High)
Data Byte from Base Address
Stop Signal
Data Transfer via Serial Interface
For each byte of data read or written, the MSB is the first bit of
the sequence.
Read from Four Consecutive Control Registers
Start Signal
Slave Address Byte (R/W Bit = Low)
Base Address Byte
If the AD9888 does not acknowledge the master device during a
write sequence, the SDA remains high so the master can
generate a stop signal. If the master device does not acknowledge
the AD9888 during a read sequence, the AD9888 interprets this
as “end of data.” The SDA remains high so the master can
generate a stop signal.
Start Signal
Slave Address Byte (R/W Bit = High)
Data Byte from Base Address
Data Byte from (Base Address + 1)
Data Byte from (Base Address + 2)
Data Byte from (Base Address + 3)
Stop Signal
Writing data to specific control registers of the AD9888 requires
that the 8-bit address of the control register of interest be written
after the slave address has been established. This control register
address is the base address for subsequent write operations. The
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REV. B
ROCHESTER [ Rochester Electronics ]
