AD9888
Sync Processing
reach 5 (1 µs/200 ns = 5). Now, when Vsync is present on the
composite sync, the counter will also count up. However, since the
Vsync signal is much longer, it will count to a higher number M.
For most video modes, M will be at least 255. So, Vsync can be
detected on the composite sync signal by detecting when the
counter counts to higher than N. The specific count that
triggers detection (T) can be programmed through the serial
Register (0FH).
Table XLII. Control of the Sync Block Muxes via the
Serial Register
Mux
Serial Bus Control Bit
Number(s) Control Bit State
Result
1 and 2
0EH: Bit 3
0FH: Bit 5
0EH: Bit 0
0
1
0
1
0
1
Pass HSYNC
Pass Sync-on-Green
Pass COAST
Pass Vsync
Pass Vsync
Pass Sync Separator
Signal
Pass Channel 0 Inputs
Pass Channel 1 Inputs
Once Vsync has been detected, there is a similar process to
detect when it goes inactive. At detection, the counter first resets
to 0, then starts counting up when Vsync goes away. Similar to
the previous case, it will detect the absence of Vsync when the
counter reaches the threshold count (T). In this way, it will
reject noise and/or serration pulses. Once Vsync is detected to
be absent, the counter resets to 0 and begins the cycle again.
3
4
5
15H: Bit 3
0
1
PCB LAYOUT RECOMMENDATIONS
Sync Slicer
The AD9888 is a high precision, high speed analog device. To
get the maximum performance out of the part, it is important to
have a well laid-out board. The following is a guide for design-
ing a board using the AD9888.
The purpose of the sync slicer is to extract the sync signal from
the green graphics channel. A sync signal is not present on all
graphics systems, only those with Sync-on-Green. The sync
signal is extracted from the green channel in a two-step process.
First, the SOG input is clamped to its negative peak (typically
0.3 V below the black level). Next, the signal goes to a comparator
with a variable trigger level, nominally 0.15 V above the clamped
level. The “sliced” sync is typically a composite sync signal
containing both Hsync and Vsync.
Analog Interface Inputs
Using the following layout techniques on the graphics inputs is
extremely important.
Minimize the trace length running into the graphics inputs. This
is accomplished by placing the AD9888 as close as possible to
the graphics (VGA) connector. Long input trace lengths are
undesirable because they will pick up more noise from the board
and other external sources.
Sync Separator
A sync separator extracts the Vsync signal from a composite sync
signal. It does this through a low-pass filter-like or integrator-like
operation. It works on the idea that the Vsync signal stays active
for a much longer time than the Hsync signal. So, it rejects any
signal shorter than a threshold value, which is somewhere between
an Hsync pulsewidth and a Vsync pulsewidth.
Place the 75 Ω termination resistors (see Figure 1) as close to
the AD9888 chip as possible. Any additional trace length
between the termination resistors and the input of the AD9888
increases the magnitude of reflections, which will corrupt the
graphics signal.
The sync separator on the AD9888 is an 8-bit digital counter
with a 5 MHz clock. It works independently of the polarity of
the composite sync signal. (Polarities are determined elsewhere
on the chip.) The basic idea is that the counter counts up when
Hsync pulses are present. But since Hsync pulses are relatively
short in width, the counter only reaches a value of N before the
pulse ends. It then starts counting down, eventually reaching 0
before the next Hsync pulse arrives. The specific value of N will
vary for different video modes, but will always be less than 255.
For example, with a 1 µs width Hsync, the counter will only
Use 75 Ω matched impedance traces. Trace impedances other
than 75 Ω will also increase the chance of reflections.
The AD9888 has very high input bandwidth (500 MHz). While
this is desirable for acquiring a high resolution PC graphics
signal with fast edges, it means that it will also capture any high
frequency noise present. Therefore, it is important to reduce the
amount of noise that gets coupled to the inputs. Avoid running
any digital traces near the analog inputs.
SDA
tBUFF
tDHO
tSTOSU
tDSU
tSTASU
tSTAH
tDAL
SCL
tDAH
Figure 23. Serial Port Read/Write Timing
REV. B
–27–
ROCHESTER [ Rochester Electronics ]
