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R2025S 参数 Datasheet PDF下载

R2025S图片预览
型号: R2025S
PDF下载: 下载PDF文件 查看货源
内容描述: 高精度I2C总线实时时钟模块 [High precision I2C-Bus Real-Time Clock Module]
分类和应用: 时钟
文件页数/大小: 47 页 / 563 K
品牌: RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
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R2025S/D  
(5) /CLEN1  
32-kHz Clock Output Bit 1  
Description  
/CLEN1  
0
1
Enabling the 32-kHz clock output  
Disabling the 32-kHz clock output  
(Default)  
Setting the /CLEN1 bit or the /CLEN2 bit (D4 in the control register 1) to 0 specifies generating clock pulses  
with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.  
Conversely, setting both the /CLEN1 and the /CLEN2 bit to 1 specifies disabling (“L”) such output.  
(6) CTFG  
Periodic Interrupt Flag Bit  
Description  
CTFG  
0
1
Periodic interrupt output = “H”  
Periodic interrupt output = “L”  
(Default)  
The CTFG bit is set to 1 when the periodic interrupt signals are output from the /INTRA pin (“L”). The  
CTFG bit accepts only the writing of 0 in the level mode, which disables (“H”) the /INTRA pin until it is  
enabled (“L”) again in the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.  
(7) WAFG,DAFG  
WAFG,DAFG  
Alarm_W Flag Bit and Alarm_D Flag Bit  
Description  
0
1
Indicating a mismatch between current time and preset alarm time  
Indicating a match between current time and preset alarm time  
(Default)  
The WAFG and DAFG bits are valid only when the WALE and DALE have the setting of 1, which is caused  
approximately 61µs after any match between current time and preset alarm time specified by the Alarm_W  
registers and the Alarm_D registers. The WAFG (DAFG) bit accepts only the writing of 0. /INTRB  
(/INTRA) pin outputs off (“H”) when this bit is set to 0. And /INTRB (/INTRA) pin outputs “L” again at the  
next preset alarm time. Conversely, setting the WAFG and DAFG bits to 1 causes no event. The WAFG  
and DAFG bits will have the reading of 0 when the alarm interrupt circuit is disabled with the WALE and  
DALE bits set to 0. The settings of the WAFG (DAFG) bit is synchronized with the output of the  
/INTRB (/INTRA) pin as shown in the timing chart below.  
Approx. 61µs  
Approx. 61µs  
WAFG(DAFG) Bit  
/INTRB(/INTRA) Pin  
Writing of 0 to  
Writing of 0 to  
WAFG(DAFG) bit  
WAFG(DAFG) bit  
(Match between  
(Match between  
(Match between  
current time and  
current time and  
current time and  
preset alarm time)  
preset alarm time)  
preset alarm time)  
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