R2025S/D
Address Mapping
Address
A3A2A1A0
Register Name
D a t a
D4
D7
D6
D5
D3
D2
D1
D0
0
0 0 0 0
Second Counter
-
*2)
-
S40
S20
S10
S8
S4
S2
S1
1
2
0 0 0 1
0 0 1 0
Minute Counter
Hour Counter
M40
-
M20
H20
P⋅/A
-
D20
-
M10
H10
M8
H8
M4
H4
M2
H2
M1
H1
-
3
4
5
0 0 1 1
0 1 0 0
0 1 0 1
Day-of-week Counter
Day-of-month Counter
Month Counter and
Century Bit
-
-
-
-
-
-
-
D8
MO8
W4
D4
MO4
W2
D2
MO2
W1
D1
MO1
D10
MO10
/19⋅20
6
7
0 1 1 0
0 1 1 1
Year Counter
Oscillation Adjustment
Register *3)
Y80
(0)
*4)
-
Y40
F6
Y20
F5
Y10
F4
Y8
F3
Y4
F2
Y2
F1
Y1
F0
8
9
A
1 0 0 0
1 0 0 1
1 0 1 0
Alarm_W
(Minute Register)
Alarm_W
(Hour Register)
Alarm_W
(Day-of-week
Register)
WM40 WM20 WM10
WM8 WM4
WH8 WH4
WW3 WW2
WM2
WM1
-
-
-
WH20
WP⋅/ A
WW5
WH10
WW4
WH2 WH1
WW1 WW0
WW6
B
C
1 0 1 1
1 1 0 0
Alarm_D
(Minute Register)
Alarm_D
(Hour Register)
-
-
-
DM40
-
DM20
DM10
DH10
-
DM8
DH8
-
DM4
DH4
DM2
DH2
DM1
DH1
DH20
DP⋅/A
-
/12⋅24
/XST
D
E
F
1 1 0 1
1 1 1 0
1 1 1 1
-
-
-
-
Control Register 1 *3) WALE
Control Register 2 *3) VDSL
DALE
VDET
/CLEN2 TEST
PON /CLEN1 CTFG WAFG DAFG
*5)
CT2
CT1
CT0
Notes:
*1) All the data listed above accept both reading and writing.
*2) The data marked with "-" is invalid for writing and reset to 0 for reading.
*3) When the PON bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment
Register, Control Register 1 and Control Register 2 excluding the /XST and PON bits.
*4) The (0) bit should be set to 0.
*5) /XST is oscillation halt sensing bit.
*6) PON is power-on reset flag.
10
RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
