R2025S/D
Register Settings
• Control Register 1 (ADDRESS Eh)
D7
WALE
WALE
0
D6
DALE
DALE
0
D5
/12⋅24
/12⋅24
0
D4
/CLEN2
/CLEN2
0
D3
TEST
TEST
0
D2
CT2
CT2
0
D1
CT1
CT1
0
D0
CT0
CT0
0
(For Writing)
(For Reading)
Default Settings *)
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
(1) WALE, DALE
WALE,DALE
Alarm_W Enable Bit, Alarm_D Enable Bit
Description
0
Disabling the alarm interrupt circuit (under the control of the settings
of the Alarm_W registers and the Alarm_D registers).
Enabling the alarm interrupt circuit (under the control of the settings
of the Alarm_W registers and the Alarm_D registers)
(Default)
(Default)
1
(2) /12⋅24
/12-24-hour Mode Selection Bit
Description
Selecting the 12-hour mode with a.m. and p.m. indications.
Selecting the 24-hour mode
/12⋅24
0
1
Setting the /12⋅24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.
24-hour mode
12-hour mode
12 (AM12)
01 (AM 1)
02 (AM 2)
03 (AM 3)
04 (AM 4)
05 (AM 5)
06 (AM 6)
07 (AM 7)
08 (AM 8)
09 (AM 9)
10 (AM10)
11 (AM11)
24-hour mode
12-hour mode
32 (PM12)
21 (PM 1)
22 (PM 2)
23 (PM 3)
24 (PM 4)
25 (PM 5)
26 (PM 6)
27 (PM 7)
28 (PM 8)
29 (PM 9)
30 (PM10)
31 (PM11)
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Setting the /12⋅24 bit should precede writing time data
(3) /CLEN2
32-kHz Clock Output Bit2
Description
/CLEN2
0
1
Enabling the 32-kHz clock output
Disabling the 32-kHz clock output
(Default)
Setting the /CLEN2 bit or the /CLEN1 bit (D3 in the control register 2) to 0 specifies generating clock pulses
with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.
Conversely, setting both the /CLEN1 and the /CLEN2 bit to 1 specifies disabling (“L”) such output.
(4) TEST
Test Bit
TEST
Description
0
1
Normal operation mode.
Test mode.
(Default)
The TEST bit is used only for testing in the factory and should normally be set to 0.
11
RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
