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R2025S 参数 Datasheet PDF下载

R2025S图片预览
型号: R2025S
PDF下载: 下载PDF文件 查看货源
内容描述: 高精度I2C总线实时时钟模块 [High precision I2C-Bus Real-Time Clock Module]
分类和应用: 时钟
文件页数/大小: 47 页 / 563 K
品牌: RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
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R2025S/D  
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or  
60sec. as follows:  
Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784 ms. For  
example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.  
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784 ms.  
Control Register 2 (Address Fh)  
D7  
VDSL  
D6  
VDET  
D5  
/XST  
D4  
PON  
D3  
/CLE  
N1  
D2  
CTFG  
D1  
WAF  
G
D0  
DAFG  
(For Writing)  
VDSL  
0
VDET  
0
/XST  
PON  
1
/CLE  
N1  
0
CTFG  
0
WAF  
G
0
DAFG  
0
(For Reading)  
Default Settings *)  
Indefinit  
e
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD  
power-on from 0 volts.  
(1) VDSL  
VDD Supply Voltage Monitoring Threshold Selection Bit  
VDSL  
Description  
0
1
Selecting the VDD supply voltage monitoring threshold setting of  
2.1v.  
Selecting the VDD supply voltage monitoring threshold setting of  
1.3v.  
(Default)  
The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.  
(2) VDET  
Supply Voltage Monitoring Result Indication Bit  
VDET  
Description  
Indicating supply voltage above the supply voltage monitoring  
threshold settings.  
0
1
(Default)  
Indicating supply voltage below the supply voltage monitoring  
threshold settings.  
Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will  
hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage  
monitoring circuit. Conversely, setting the VDET bit to 1 causes no event.  
(3) /XST  
Oscillation Halt Sensing Monitor Bit  
/XST Description  
0
1
Sensing a halt of oscillation  
Sensing a normal condition of oscillation  
The /XST accepts the reading and writing of 0 and 1. The /XST bit will be set to 0 when the oscillation halt  
sensing. The /XST bit will hold 0 even after the restart of oscillation.  
(4) PON  
Power-on-reset Flag Bit  
PON  
Description  
0
1
Normal condition  
Detecting VDD power-on -reset  
(Default)  
The PON bit is for sensing power-on reset condition.  
* The PON bit will be set to 1 when VDD power-on from 0 volts. The PON bit will hold the setting of 1 even  
after power-on.  
* When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control  
Register 1, and Control Register 2, except /XST and PON. As a result, /INTRA and /INTRB pins stop  
outputting.  
* The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event.  
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