RT5735
Top layer
2nd layer
AGND and PGND connect
together at negative of Cin
to reduce noise.
Vias can help to reduce power trace and improve
thermal dissipation. PGND pins connect top layer
and 2nd layer directly for thermal dissipation.
Vout connects to FB
pin from 2nd layer.
SCL
A3
VSEL
A1
EN
A2
FB
A4
PG/P
GND
B3
GND
SDA
B1
PGND
B4
PGND
B2
PGND
C2
PGND
C3
PGND
C4
AGND
C1
AVDD
D1
PVDD
D2
LX
D3
LX
D4
PVDD
E1
PVDD
E2
LX
E3
LX
E4
WL-CSP-20B 1.6X2 (BSC)
Vout connects to FB
pin from 2nd layer
VIN
VOUT
Input capacitor must be placed as close
to the IC as possible. Suggest layout
trace wider for thermal dissipation .
SW should be connected to inductor by wide and short
trace. Keep sensitive components away from this trace.
Suggest layout trace wider for thermal dissipation .
Figure 5. PCB Layout Guide
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation
www.richtek.com
20
DS5735-00 August 2014
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
