RT5735
Thermal Considerations
Layout Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature.
The maximum power dissipation can be calculated by
the following formula :
For best performance of the RT5735, the following
layout guidelines must be strictly followed.
Input capacitor must be placed as close to the IC as
possible.
SW should be connected to inductor by wide and
short trace. Keep sensitive components away from
this trace.
PD(MAX) = (TJ(MAX) TA) / JA
Keep every trace connected to pin as wide as
possible for improving thermal dissipation.
where TJ(MAX) is the maximum junction temperature, TA
is the ambient temperature, and JA is the junction to
ambient thermal resistance.
For recommended operating condition specifications,
the maximum junction temperature is 125C. The
junction to ambient thermal resistance, JA, is layout
dependent. For WL-CSP-20B 1.6x2 (BSC) package, the
thermal resistance, JA, is 55C/W on a standard
JEDEC 51-7 four-layer thermal test board. The
maximum power dissipation at TA = 25C can be
calculated by the following formula :
PD(MAX) = (125C 25C) / (55C/W) = 1.8W for
WL-CSP-20B 1.6x2 (BSC) package
The maximum power dissipation depends on the
operating ambient temperature for fixed TJ(MAX) and
thermal resistance, JA. The derating curve in Figure 4
allows the designer to see the effect of rising ambient
temperature on the maximum power dissipation.
2.5
Four-Layer PCB
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 4. Derating Curve of Maximum Power
Dissipation
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is a registered trademark of Richtek Technology Corporation
DS5735-00 August 2014
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