RT5735
Register
Name
Register
Address
b[7]
(MSB)
b[0]
(LSB)
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
Meaning ENVSEL0
Vout_VSEL0[6:0]
0
PROGVSE
L0
0x11 Default
Read/Write
1
0
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EN Pin Gating for VSEL internal signal= Low
ENVSEL0
0 : Disabled
1 : Enabled
VID Table satisfy :
SEL[6:0] = 1111111 : VOUT = 1393.75mV
…
Vout_VSEL0[6:0]
SEL[6:0] = 0010000 : VOUT = 0.7V (default)
…
SEL[6:0] = 0000000 : 0.6V
6.25mV step for DCDC, VOUT = 600mV + 6.25mV x SEL
Register
Name
Register
Address
b[7]
(MSB)
b[0]
(LSB)
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
Meaning
RESV
DISCHG
0
RESV
PGDVS PGDCDC
PGOOD 0x12 Default
Read/Write
0
0
0
0
0
0
0
R
R
R
R/W
R
R
R/W
R/W
RESV
Reserved bits
Active discharge bit enabling
0 : Discharge path disabled
1 : Discharge path enabled
DISCHG
RESV
Reserved bits
Power good active on DVS
0 : Disabled
PGDVS
1 : Enabled
Power good enabling
0 : Disabled
PGDCDC
1 : Enabled
Register
Name
Register
Address
b[7]
(MSB)
b[0]
(LSB)
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
Meaning
Reserved
DVS_UP[2:0]
Reserved
TIME
0x13 Default
Read/Write
RESV
0
0
0
1
1
0
0
1
R
R
R
R/W
R/W
R/W
R
R
Reserved bits
DVS slew rate for up
000 : 64mV/S
001 : 16mV/S
010 : 32mV/S
011 : 8mV/S
100 : 4mV/S
101 : 4mV/S
110 : 32mV/S
111 : 8mV/S
DVS_UP[2:0]
RESV
Reserved bits
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation
DS5735-00 August 2014
www.richtek.com
17
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