RT3669EA
the ADC timing and generates the digital code of the
VID for VSEN voltage.
Loop Control Protection Logic
Loop control protection logic detects EN and UVLO
signals to initiate the soft-start function, and the
PGOOD and VRHOT_L will be controlled after the
soft-start is finished. When VRHOT indication event
occurs, the VRHOT_L pin voltage will be pulled low.
DAC
The DAC receives VID codes from the SVI2 control
logic to generate an internal reference voltage (VSET)
for controller.
POWER_MUX
Soft-Start and Slew-Rate Control
This block controls the slew rate of the internal
reference voltage when output voltage changes.
Error Amplifier
Error amplifier generates COMP signal by the
difference between VSET and FB.
Offset Cancellation
This block cancels the output offset voltage from
voltage ripple and current ripple to achieve accurate
output voltage.
UVLO
Detect the VCC pin voltage for under voltage lockout
protection and power on reset operation.
PWM CMP
The PWM comparator compares COMP signal and
current feedback signal to generate a signal for
TONGEN.
TONGEN
This block generates an on-time pulse which high
interval is based on the on-time setting and current
balance.
If MUX_CTRL = High, then S5_OUT = VSEN_NB_IN.
If MUX_CTRL = Low, S5_OUT = VSEN_NB_IN or
LDO_OUT, refer to MUX description of Application
Information.
LDO
The LDO regulates its output voltage (LDO_OUT) with
the fixed reference voltage (0.4V). And the external
resistors connected to FBA pin can be adjust to
change the output voltage.
RAMP
The Ramp generator is designed to improve noise
immunity and reduce jitter.
OC/OV/UV
VSEN and output current are sensed for over current,
over voltage and under voltage protection.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS3669EA-06
August 2019
www.richtek.com
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