RT3669EA
Functional Block Diagram
VRHOT_L
PWROK
PGOOD
VDDIO
VSEN
TSEN
SET1
VCC
SVC
SVD
SVT
EN
IMONI
UVLO
GND
MUX
SVI2 Interface
Configuration Registers
Control Logic
Loop Control
Protection Logic
ADC
From Control Logic
RGND
DAC
ERROR
AMP
AI_GFX
QR_TH
TONSET
OFFSET
PHOCP_TH
VIN
Soft Start&
Slew Rate Control
FB
COMP
1.867m
ISEN1P
ISEN1N
VREF_PINSET
IMON
+
-
+
-
VSET
+
-
Offset
Cancellation
+
+
-
PWM
CMP
QR_TH
BOOT
TON
GEN
PWM
Driver
UGATE
PHASE
LGATE
0.75 x AI_VDD
RAMP
TONSET
IMONI
VSEN
OV/UV
OC
To Protection Logic
LDO
+
Driver
POR
PVCC
+
OCP_SPIKE
MUX_CTRL
VSEN_NB_IN
40mV
LDO_OUT
-
VCC
0.4V
CMP
+
-
OP
LDO_VIN
-
10mV
+
-
+
-
LDO_OUT
VSEN_NB_IN
0
POWER
_MUX
1
LDO_OUT
FBA
S5_OUT
Operation
The RT3669EA adopts G-NAVP
TM
(Green Native AVP)
which is Richtek's proprietary topology derived from
finite DC gain of EA amplifier with current mode control,
making it easy to set the droop to meet all AMD GFX
requirements of AVP (Adaptive Voltage Positioning).
The G-NAVP
TM
MUX and ADC
The MUX supports the inputs from SET1, TSEN,
IMONI and VSEN. The ADC converts these analog
signals to digital codes for reporting or performance
adjustment.
SVI2 Interface/Configuration Registers/Control
Logic
The SVI2 interface uses the SVC, SVD, and SVT pins
to communicate with GFX. The configuration registers
save the digital data from ADC output for reporting or
performance adjustment. The Control Logic controls
is a registered trademark of Richtek Technology Corporation.
controller is one type of current mode
constant on-time control with DC offset cancellation.
The approach can not only improve DC offset problem
for increasing system accuracy but also provide fast
transient response. When current feedback signal
reaches COMP signal, it generates an on-time width
to achieve PWM modulation.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
www.richtek.com
4
DS3669EA-06
August 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
