RT3669EA
Pin No.
13
Pin Name
VCC
Pin Function
Controller power supply. Connect this pin to 5V and place a decoupling
capacitor 2.2F at least. The decoupling capacitor is as close controller as
possible.
System power good input. If PWROK is low, the SVI interface is disabled and
VR returns to BOOT-VID state with initial load-line slope and initial offset. If
PWROK is high, the SVI interface is running and the DAC decodes
the
received serial VID codes to determine the output voltage.
Serial VID clock input.
Serial VID data input. This pin is a serial data line.
Serial VID telemetry output from VR. This pin is a push-pull output.
Processor memory interface power rail and serves as the reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
This pin is connected to the output of VDDNB controller.
FCH power output.
LDO output.
LDO output voltage feedback input.
MUX control input. When the pin pulled high, the S5_OUT output voltage is
forced to VSEN_NB_IN pin voltage. If the pin pulled low, the S5_OUT output
voltage is forced to VSEN_NB_IN pin voltage when the VSEN_NB_IN
voltage is greater than LDO_OUT voltage; otherwise, the S5_OUT voltage is
forced to LDO_OUT pin voltage.
LDO power input.
Bootstrap supply of GFX controller for high-side MOSFET. This pin powers
high-side MOSFET driver.
Upper gate driver output of GFX controller. Connect this pin to the gate input
of high-side MOSFET.
Switch nodes of high-side driver for GFX controller. Connect this pin to high-
side MOSFET Source together with the low-side MOSFET Drain and the
inductor.
Driver power supply. Connect this pin to GND by the 2.2F ceramic capacitor
at least. The decoupling capacitor is as close controller as possible.
Lower Gate Driver Output of GFX Controller. Connect this pin to the gate
input of low-side MOSFET.
No internal connection.
Power good indicator for the GFX controller. This pin is an open drain output.
Controller enable input pin.
Ground. The exposed pad must be soldered to a large PCB and connected
to GND for maximum power dissipation.
14
PWROK
15
16
17
18
19
20
21
22
SVC
SVD
SVT
VDDIO
VSEN_NB_IN
S5_OUT
LDO_OUT
FBA
23
MUX_CTRL
24
25
26
27
28
29
30
31
32
LDO_VIN
BOOT
UGATE
PHASE
PVCC
LGATE
NC
PGOOD
EN
33 (Exposed Pad) GND
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS3669EA-06
August 2019
www.richtek.com
3
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
