RF2052
CFG1 (OOh) - Operational Configuration Parameters
#
15
14
13
12
11
10
9
Bit Name
LD_EN
Default
Function
1
0
0
0
0
0
0
1
1
1
0
0
0
0
9
Enable lock detector circuitry
LD_LEV
Modify lock range for lock detector
TVCO(4:0)
VCO warm-up time=TVCO/(F *256)
REF
1
C
0
8
PDP
Phase detector polarity: 0=positive, 1=negative
Active loop filter enable, 1=Active 0=Passive
7
LF_ACT
CPL(1:0)
6
Charge pump leakage current: 00=no leakage, 01=low leakage, 10=mid leakage, 11=high
leakage
5
4
CT_POL
Polarity of VCO coarse-tune word: 0=positive, 1=negative
3
2
EXT_VCO
0=Normal operation 1=external VCO (VCO3 disabled, KV_CAL and CT_CAL must be dis-
abled)
1
0
FULLD
0
0
0=Half duplex, mixer is enabled according to MODE pin, 1=Full duplex, both mixers enabled
0=High charge pump current, 1=low charge pump current
CP_LO_I
CFG2 (O1h) - Mixer Bias and PLL Calibration
#
15
14
13
12
11
10
9
Bit Name
MIX1_IDD
Default
Function
1
0
0
0
1
1
0
0
0
1
0
1
1
0
0
0
8
This register is not used for the RF2052.
MIX1_VB
This register is not used for the RF2052.
C
5
8
MIX2_IDD
Mixer 2 current setting: 000=0mA to 111=35mA in 5mA steps
Mixer 2 voltage bias
8
7
MIX2_VB
6
5
4
KV_RNG
Sets accuracy of voltage measurement during KV calibration: 0=8bits, 1=9bits
Number of averages during CT cal
3
NBR_CT_AVG
2
1
NBR_KV_AVG
Number of averages during KV cal
0
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DS140110
RFMD [ RF MICRO DEVICES ]
