RF2052
CFG3 (O2h) - PLL Calibration
#
15
14
13
12
11
10
9
Bit Name
TKV1
Default
Function
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
Settling time for first measurement in LO KV compensation
TKV2
4
0
4
Settling time for second measurement in LO KV compensation
8
7
6
5
4
3
FLL_FACT
Default setting 01. Needs to be set to 00 for N<28. This case can arise when higher phase
detector frequencies are used.
2
1
CT_CPOL
REFSTBY
0
Reference oscillator standby mode 0=XO is off in standby mode, 1=XO is on in standby mode
CFG4 (O3h) - Crystal Oscillator and Reference Divider
#
15
14
13
12
11
10
9
Bit Name
CLK_DIV
Default
Function
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
Reference divider, divide by 2 (010) to 7 (111) when reference divider is enabled
CLK_DIV_BYPASS
XO_CT
Reference divider enabled=0, divider bypass (divide by 1)=1
8
0
F
Crystal oscillator coarse tune (approximately 0.5pF steps from 8pF to 16pF)
8
7
XO_I2
XO_I1
XO_CR_S
TCT
Crystal oscillator current setting
6
5
Crystal oscillator additional fixed capacitance (approximately 0.25pF)
Duration of coarse tune acquisition
4
3
2
1
0
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