RF2052
Start-up
When starting up and following device reset then REFSTBY=0, REFSTBY should be asserted high approximately 500s before
ENBL is taken high. This is to allow the XO to settle and will depend on XO characteristics. The various calibration routines will
also take some time depending on whether they are enabled or not. Coarse tuning calibration takes about 50s and VCO tun-
ing gain compensation takes about 100s. Additionally, time for the PLL to settle will be required. All of these timings will be
dependant upon application specific factors such as loop filter bandwidth, reference clock frequency, XO characteristics and
so on. The fastest turn-on and lock time will be obtained by leaving REFSTBY asserted high, disabling all calibration routines,
and setting the PLL loop bandwidth as wide as possible.
The device can be reset into its initial state (default settings) at any time by performing a hard reset. This is achieved by setting
the RESETB pin low for at least 100ns.
Setting Up Device Operation
The device offers a number of operating modes which need to be set up in the device before it will work as intended. This is
achieved as follows.
Set-up device
operation
1
When setting up the device it is necessary to decide if
an active or passive loop filter will be used in the
Disable active
loop filter?
LF_ACT
Set to 0
phase locked loop. The LF_ACT bit is located in the
CFG1 register and is active by default. Set the phase
detector polarity bit in CFG1since the active filter
inverts the loop filter voltage.
Yes
Default
The mixer linearity setting is then selected. The default
value is 4 with 1 being the lowest setting and 5 the
highest. The MIX2_IDD bits are located in the CFG2
register.
Mixer
linearity
Program
MIX2_IDD
Internal
capacitors
used to set
Xtal load
The internal crystal loading capacitors are also
programmed to present the correct load to the crystal.
The capacitance internal to the chip can be varied
from 8-16pF in 0.25pF steps (default=10pF). The
reference divider must also be set to determine the
phase detector frequency (default=1). These bits are
located in the CFG4 register.
Program XO_CT,
XO_CR_S and
CLK_DIV
Set-up complete
2
Three registers need to be written, taking 3.9us at the maximum clock speed. If the device is used with an active filter in sim-
plex operation it will not be necessary to program CFG1 reducing the programming time to 2.6us.
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