3.3 PLL
The PLL channel is set with the Ch_Num bits in configuration register 0x00. In transmit mode, the PLL is normally
turned on with the falling edge of the MODE input. The TRC104 transmits the data after the PLL locks and the
power amplifier has ramped up to its programmed level. PLL lock time is typically 170 µs. It is possible to enable
and lock the PLL before the falling edge of MODE input. This can provides a shorter transition time to transmit.
The PLL pre-start delay time is adjustable from 20 µs up to 5 ms. The value of PLL_ON in register 0x14 sets this
time. The pre-start delay timer is triggered on the rising edge of MODE as shown in Figure 5. The value of
PLL_ON determines the delay time from the rising edge of MODE before the PLL is enabled. Care must be taken
to carefully calculate the write time of the data packet into the transmit FIFO so that the TRC104 does not enable
the transmitter and begin sending data before the data packet is fully written to the FIFO, in which case the
TRC104 will discard the current packet.
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Figure 5
3.4 Crystal Oscillator
At the 1 Mb/s RF data rate, the TRC104 uses a 16 MHz crystal. At the 250 kb/s RF data rate, the TRC104 can
use any one of five standard crystal frequencies: 4, 8, 12, 16, or 20 MHz. The crystal frequency is configured by
setting the FXTAL bits in register 0x01. At the 250 kb/s data rate, the TRC104’s power consumption is reduced by
using one of the lower crystal frequencies. The total load capacitance CL seen between the XTLIN and XTLOUT
terminals is composed primarily of CIN and COUT in series, as shown if Figure 6:
CL = 1/((1/CIN) + (1/COUT) ) + CSTRAY, where CSTRAY is the capacitance associated with the PCB layout
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Figure 6
A typical value for CSTRAY is 1 pF. The values of CIN and COUT should be approximately equal and chosen so that
CL matches the load capacitance specified for the crystal. A typical CL value for a 16 MHz crystal is 12 pF. The
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TRC104 - 08/13/09
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