欢迎访问ic37.com |
会员登录 免费注册
发布采购

TRC104 参数 Datasheet PDF下载

TRC104图片预览
型号: TRC104
PDF下载: 下载PDF文件 查看货源
内容描述: 2.4 GHz射频收发器 [2.4 GHz RF Transceiver]
分类和应用: 射频
文件页数/大小: 33 页 / 1023 K
品牌: RFM [ RF MONOLITHICS, INC ]
 浏览型号TRC104的Datasheet PDF文件第6页浏览型号TRC104的Datasheet PDF文件第7页浏览型号TRC104的Datasheet PDF文件第8页浏览型号TRC104的Datasheet PDF文件第9页浏览型号TRC104的Datasheet PDF文件第11页浏览型号TRC104的Datasheet PDF文件第12页浏览型号TRC104的Datasheet PDF文件第13页浏览型号TRC104的Datasheet PDF文件第14页  
3.3 PLL  
The PLL channel is set with the Ch_Num bits in configuration register 0x00. In transmit mode, the PLL is normally  
turned on with the falling edge of the MODE input. The TRC104 transmits the data after the PLL locks and the  
power amplifier has ramped up to its programmed level. PLL lock time is typically 170 µs. It is possible to enable  
and lock the PLL before the falling edge of MODE input. This can provides a shorter transition time to transmit.  
The PLL pre-start delay time is adjustable from 20 µs up to 5 ms. The value of PLL_ON in register 0x14 sets this  
time. The pre-start delay timer is triggered on the rising edge of MODE as shown in Figure 5. The value of  
PLL_ON determines the delay time from the rising edge of MODE before the PLL is enabled. Care must be taken  
to carefully calculate the write time of the data packet into the transmit FIFO so that the TRC104 does not enable  
the transmitter and begin sending data before the data packet is fully written to the FIFO, in which case the  
TRC104 will discard the current packet.  
P
L
L
P
r
e
-
s
t
a
r
t
T
i
m
i
n
g
M
O
D
E
P
L
L
O
F
F
P
L
L
L
O
C
K
I
N
G
P
L
L
O
N
P
L
L
O
F
F
P
D
D
L
L
S
t
a
t
e
R
F
D
a
t
a
T
r
a
n
s
m
i
s
s
i
o
n
a
t
a
D
E
L
A
Y
E
L
A
Y
:
P
r
e
-
s
t
a
r
t
d
e
l
a
y
i
n
t
e
r
v
a
l
Figure 5  
3.4 Crystal Oscillator  
At the 1 Mb/s RF data rate, the TRC104 uses a 16 MHz crystal. At the 250 kb/s RF data rate, the TRC104 can  
use any one of five standard crystal frequencies: 4, 8, 12, 16, or 20 MHz. The crystal frequency is configured by  
setting the FXTAL bits in register 0x01. At the 250 kb/s data rate, the TRC104s power consumption is reduced by  
using one of the lower crystal frequencies. The total load capacitance CL seen between the XTLIN and XTLOUT  
terminals is composed primarily of CIN and COUT in series, as shown if Figure 6:  
CL = 1/((1/CIN) + (1/COUT) ) + CSTRAY, where CSTRAY is the capacitance associated with the PCB layout  
T
R
C
1
0
4
C
r
y
s
t
a
l
O
s
c
i
l
l
a
t
o
r
I
m
p
l
e
m
e
n
t
a
t
i
o
n
9
8
C
C
O
U
T
I
N
Figure 6  
A typical value for CSTRAY is 1 pF. The values of CIN and COUT should be approximately equal and chosen so that  
CL matches the load capacitance specified for the crystal. A typical CL value for a 16 MHz crystal is 12 pF. The  
www.RFM.com E-mail: info@rfm.com  
©2009 by RF Monolithics, Inc.  
Technical support +1.800.704.6079  
Page 10 of 33  
TRC104 - 08/13/09