3 Architecture
The TRC104 is a single-chip FSK transceiver that operates in the worldwide 2.4 GHz ISM band. The TRC104’s
highly integrated architecture requires a minimum of external components. Advanced features including the
TX/RX FIFO and the burst packet data mode significantly reduce the TRC104’s load on the host microcontroller.
As shown in Figure 2, the TRC104 utilizes a dual-conversion superheterodyne receiver architecture with an
image-reject second mixer. The VCO operates directly at the output frequency when transmitting, and is
modulated by a Gaussian-filtered bit stream.
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3.1 RF Port
The TRC104 has a differential RF port that is capable of delivering the required transmitter output power at low
supply voltages. The differential RF port also provides common mode signal rejection to enhance receiver
interference immunity. A simple L-C balun can be used to convert the differential port to a single-ended output to
drive an unbalanced antenna, as shown in Figure 3.
3.2 Transmitter Power Amplifier
The power amplifier controls the output power level of the transmitter. The power amplifier has four programmable
power levels. The power level is set by the PWR bits in configuration register 0x01.
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Page 8 of 33
TRC104 - 08/13/09
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