RX62Nグループ、RX621グループ
5. Electrical Characteristics
5.3.3
Bus Timing
Table 5.10
Bus Timing [176-pin LFBGA/145-pin TFLGA/144-pin LQFP]
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V
ICLK = 8 to 100MHz, BCLK = 8 to 100MHz, SDCLK = 8 to 50MHz
Ta = -40 to +85C
Output load conditions: VOH = VCC×0.5, VOL = VCC×0.5, IOH = -1.0mA, IOL = 1.0mA, C = 30pF
Item
Symbol
tAD
Min.
Max.
15
Unit
ns
Test Conditions
—
Address delay time
Figure 5.10 to Figure 5.13
—
—
—
15
0.0
—
—
0
15
15
15
—
—
15
15
—
—
—
15
15
15
15
—
—
15
—
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Byte control delay time
CS# delay time
tBCD
tCSD
RD# delay time
tRSD
Read data setup time
tRDS
Read data hold time
tRDH
WR# delay time
tWRD
tWDD
tWDH
tWTS
Write data delay time
Write data hold time
15
0.0
1
WAIT# setup time
Figure 5.14
WAIT# hold time
tWTH
tAD2
Address delay time 2 (SDRAM)
CS# delay time 2 (SDRAM)
DQM delay time (SDRAM)
CKE delay time (SDRAM)
Read data setup time 2 (SDRAM)
Read data hold time 2 (SDRAM)
Write data delay time 2 (SDRAM)
Write data hold time 2 (SDRAM)
WE# delay time (SDRAM)
RAS# delay time (SDRAM)
CAS# delay time (SDRAM)
Figure 5.22 to Figure 5.28
1
tCSD2
tDQMD
tCKED
tRDS2
tRDH2
tWDD2
tWDH2
tWED
tRASD
tCASD
1
1
12
0
—
1
1
1
1
R01UH0033JJ0110 Rev.1.10
2010.12.24
Page 98 of 1931
RENESAS [ RENESAS TECHNOLOGY CORP ]
