R8C/13 Group
11. Watchdog Timer
11. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. Figure 11.1 shows the watchdog timer
block diagram.The watchdog timer contains a 15-bit counter which counts down the clock derived by
dividing the CPU clock using the prescaler. Whether to generate a watchdog timer interrupt request or
apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after
reaching the terminal count can be selected using the PM12 bit in the PM1 register. The PM12 bit can
only be set to “1” (reset). Once this bit is set to “1”, it cannot be set to “0” (watchdog timer interrupt) in a
program. Refer to Section 5.3, “Watchdog Timer Reset” for details.
The divide-by-N value for the prescaler can be chosen to be 16 or 128 with the WDC7 bit in the WDC
register. The period of watchdog timer can be calculated as given below. The period of watchdog timer is,
however, subject to an error due to the prescaler.
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
Watchdog timer period =
CPU clock
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 32.8 ms.
Figure 11.2 shows the OFS, the WDC, the WDTR and the WDTS registers. The watchdog timer opera-
tion after reset can be selected using the WDTON bit in the option function select register (0FFFF16
address).
• When the WDTON bit is “0” (the watchdog timer is started automatically after reset), the watchdog
timer and the prescaler both start counting automatically after reset.
• When the WDTON bit is “1” (the watchdog timer is inactive after reset), the watchdog timer and the
prescaler both are inactive after reset, so that the watchdog timer is activated to start counting by
writing to the WDTS register.
The WDTON bit can not be changed in a program. When setting the WDTON bit, write “0” into bit 0 of
0FFFF16 address using a flash writer. The watchdog timer is nitialized by writing to the WDTR register
and the counting continues.
In stop mode and wait mode, the watchdog timer and the prescaler are stopped. Counting is resumed
from the held value when the modes or state are released.
Prescaler
PM12 = 0
Watchdog timer
interrupt request
WDC7 = 0
1/16
Watchdog timer
WDC7 = 1
1/128
CPU clock
PM12 = 1
Watchdog
timer Reset
Set to
“7FFF16
”
Write to WDTR register
Internal
reset signal
Figure 11.1 Watchdog Timer Block Diagram
Rev.1.20 Jan 27, 2006 page 68 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
