R8C/13 Group
6. Clock Generating Circuit
Oscillation stop detection register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
OCD
Address
000C16
After reset
0416
0 0 0 0
Bit symbol
OCD0
Bit name
Function
RW
RW
b1 b0
Oscillation stop
detection enable bit
0 0: The function is disabled(4)
0 1: Do not set
1 0: Do not set
1 1: The function is enabled(7)
0: Select main clock(7)
1: Select on-chip oscillator clock(2)
OCD1
OCD2
System clock select bit(6)
RW
RO
RW
0: Main clock on
1: Main clock off
Clock monitor bit(3, 5)
Reserved bit
OCD3
Set to "0"
(b7-b4)
NOTES:
1. Set the PRC0 bit in the PRCR register to “1” (write enable) before rewriting this register.
2. The OCD2 bit is set to “1” (selecting on-chip oscillator clock) automatically if a main clock oscillation stop
is detected while the OCD1 to OCD0 bits are set to “11 ” (oscillation stop detection function enabled). If
2
the OCD3 bit is set to “1” (main clock stops), the OCD2 bit remains unchanged when trying to write “0”
(main clock selected).
3. The OCD3 bit is enabled when the OCD1 to OCD0 bits are set to “112” (oscillation stop detection function
enabled).
4. The OCD1 to OCD0 bits should be set to “002” (oscillation stop detection function disabled) before
entering stop mode or on-chip oscillator (main clock stops).
5. The OCD3 bit remains set to “0” (main clock on) if the OCD1 to OCD0 bits are set to “002”.
6. The CM14 bit goes to “0” (low-speed on-chip oscillator on) if the OCD2 bit is set to “1” (on-chip oscillator
clock selected).
7. Refer to Figure 6.7 “switching clock source from low-speed on-chip oscillator to main clock” for the
switching procedure when the main clock re-oscillates after detecting an oscillation stop.
Figure 6.3 OCD Register
Rev.1.20 Jan 27, 2006 page 32 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
