R8C/13 Group
17.4 CPU Rewrite Mode
17.4.4 Status Register
The status register indicates the operating status of the flash memory and whether an erase or pro-
gramming operation terminated normally or in error. The status of the status register can be known by
reading the FMR00, FMR06, and FMR07 bits in the FMR0 register.
Table 17.5 lists the status register.
In EW0 mode, the status register can be read in the following cases:
(1) When a given address in the user ROM area is read after writing the Read Status Register com-
mand
(2) When a given address in the user ROM area is read after executing the Program or Block Erase
command but before executing the Read Array command.
• Sequence Status (SR7 and FMR00 Bits )
The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto
programming and auto erase, and is set to “1” (ready) at the same time the operation finishes.
• Erase Status (SR5 and FMR07 Bits)
Refer to Section 17.4.5, “Full Status Check.”
• Program Status (SR4 and FMR06 Bits)
Refer to Section 17.4.5, “Full Status Check.”
Table 17.5 Status Register
Value
after
reset
Status
register
bit
FMR0
register
bit
Contents
Status name
"0"
Busy
-
"1"
Ready
-
SR7 (D
SR6 (D
SR5 (D
SR4 (D
SR3 (D
SR2 (D
SR1 (D
SR0 (D
7)
6)
5)
4)
3)
2)
1)
0)
Sequencer status
Reserved
FMR00
1
Erase status
Program status
Reserved
FMR07
FMR06
Terminated normally
Terminated normally
0
0
Terminated in error
Terminated in error
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
• D7 to D0: Indicates the data bus which is read out when the Read Status Register command is executed.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are set to “0” by executing the Clear Status Register com-
mand.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the Program and Block Erase commands are not
accepted.
Rev.1.20 Jan 27, 2006 page 179 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
