R8C/13 Group
12.4 Timer (Timer C)
Timer C control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCC1
Address
009B16
After reset
0016
RW
RW
Bit symbol
TCC10
Function
Bit name
b1 b0
INT3 input filter select bit(1)
0 0: No filter
0 1: Filter with f
1 0: Filter with f
1
8
sampling
sampling
TCC11
TCC12
RW
RW
1 1: Filter with f32 sampling
0: No reload (free-run)
1: Set TC register to “000016” at
compare 1 match
Timer C counter reload
select bit(3)
0: Capture
Compare 0/Capture select
bit(2)
TCC13
TCC14
(input capture mode)(3)
1: Compare 0 output
(output compare mode)
RW
RW
b5 b4
Compare 0 output mode
select bit(3)
0 0: CMP output remains unchanged
even when compare 0 signal
matched
0 1: CMP output is reversed when
compare 0 signal is matched
1 0: CMP output is set to low when
compare 0 signal is matched
1 1: CMP output is set to high when
compare 0 signal is matched
TCC15
TCC16
b7 b6
Compare 1 output mode
select bit(3)
RW
0 0: CMP output remains unchanged
even when compare 1 signal
matched
0 1: CMP output is reversed when
compare 1 signal is matched
1 0: CMP output is set to low when
compare 1 signal is matched
1 1: CMP output is set to high when
compare 1 signal is matched
TCC17
NOTES:
1. Input is recognized only when the same value from INT3 pin is sampled three times in succession.
2. The TCC00 bit in the TCC0 register should be set to “0” (count stop) when rewriting the TCC13 bit.
3. The TCC12 and TCC14 to TCC17 should be set to “0” when the TCC13 bit is “0” (input capture mode).
Timer C output control register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCOUT
Address
00FF16
After reset
0016
RW
Bit symbol
TCOUT0
Function
0: Disable CMP output from CMP0
1: Enable CMP output from CMP00
Bit name
0
CMP output enable bit 0
RW
RW
0: Disabe CMP output from CMP0
1: Enable CMP output from CMP0
1
1
CMP output enable bit 1
CMP output enable bit 2
CMP output enable bit 3
TCOUT1
TCOUT2
0: Disable CMP output from CMP0
2
RW
1: Enable CMP output from CMP0
2
0: Disable CMP output from CMP10
1: Enable CMP output from CMP10
RW
RW
RW
TCOUT3
TCOUT4
TCOUT5
0: Disable CMP output from CMP1
1
CMP output enable bit 4
CMP output enable bit 5
CMP output reverse bit 0
1: Enable CMP output from CMP1
1
0: Disable CMP output from CMP1
2
1: Enable CMP output from CMP1
0: Not reverse CMP output from
2
TCOUT6
TCOUT7
CMP0
1: Reverse CMP output from
CMP 0 to CMP0
0 to CMP02
RW
RW
0
2
0: Not reverse CMP output from
CMP1 to CMP1
1: Reverse CMP output from
CMP1 to CMP1
CMP output reverse bit 1
0
2
0
2
NOTES:
1. Set the bits which are not used for the CMP output to “0”.
Figure 12.32 TCC1 Register and TCOUT Register
Rev.1.20 Jan 27, 2006 page 104 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
