M66291GP/HP
Address
b15
H’38
H’3A
H’3C
H’3E
H’40
H’42
H’44
H’46
H’48
H’4A
H’4C
H’4E
H’50
H’52
H’54
H’56
H’58
H’5A
H’5C
H’5E
H’60
H’62
H’64
H’66
H’68
H’6A
H’6C
H’6E
H’70
H’72
H’74
H’76
+1 address
b8 b7
(Reserved)
(Reserved)
(Reserved)
(Reserved)
+0 address
b0
H/W
Reset state
S/W
USB bus
CPU_FIFO Select Register
CPU_FIFO Control Register
CPU_FIFO Data Register
SIE_FIFO Status Register
D0_FIFO Select Register
D0_FIFO Control Register
D0_FIFO Data Register
DMA0_Transaction Count Register
D1_FIFO Select Register
D1_FIFO Control Register
D1_FIFO Data Register
DMA1_Transaction Count Register
FIFO Status Register
Port Control Register
Port Data Register
Drive Current Adjust Register
EP1 Configuration Register 0
EP1 Configuration Register 1
EP2 Configuration Register 0
EP2 Configuration Register 1
EP3 Configuration Register 0
EP3 Configuration Register 1
EP4 Configuration Register 0
EP4 Configuration Register 1
EP5 Configuration Register 0
EP5 Configuration Register 1
EP6 Configuration Register 0
EP6 Configuration Register 1
H'0000
H'0800
????
H'0000
H'0000
H'0800
????
H'0000
H'0000
H'0800
????
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0040
H'0000
H'0040
H'0000
H'0040
H'0000
H'0040
H'0000
H'0040
H'0000
H'0040
-
-
-
-
-
-
-
-
-
-
-
-
H'0000
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Figure 2.2 Register Mapping (2)
Rev1.01
2004.11.01
page 11 of 122