7th.July.2000 Ver. 1.1
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Write cycle ( S
1
control mode)
t
CW
A
0~16
t
su (A)
t
su (S1)
t
rec (W)
S
1
S
2
(Note 5)
(Note 7)
(Note 5)
W
(Note 6)
(Note 5)
(Note 5)
t
su (D)
DATA IN
STABLE
t
h (D)
DQ
1~8
Write cycle (S
2
control mode)
t
CW
A
0~16
S
1
(Note 5)
(Note 5)
t
su (A)
S
2
t
su (S2)
t
rec (W)
(Note 7)
W
(Note 5)
(Note 6)
(Note 5)
t
su (D)
DATA IN
STABLE
t
h (D)
DQ
1~8
Note 5: Hatching indicates the state is "don't care".
6: Writing is executed while S
2
high overlaps S
1
and W low.
7: When the falling edge of W is simultaneously or prior to the falling edge of S
1
or rising edge of S
2
, the outputs are maintained in the high impedance state.
8: Don't apply inverted phase signal externally when DQ pin is output mode.
6
RENESAS [ RENESAS TECHNOLOGY CORP ]
