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M5M5V108DFP-70H 参数 Datasheet PDF下载

M5M5V108DFP-70H图片预览
型号: M5M5V108DFP-70H
PDF下载: 下载PDF文件 查看货源
内容描述: 1048576 - BIT ( 131072 -字×8位)的CMOS静态RAM [1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 9 页 / 117 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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7th.July.2000 Ver. 1.1
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(Ta=0~70°C, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
V
CC
................................. 2.7~3.6V
Input pulse level ............. V
IH
=2.2V,V
IL
=0.4V
Input rise and fall time ..... 5ns
Reference level ............... V
OH
=V
OL
=1.5V
Output loads ................... Fig.1, C
L
=30pF
C
L
=5pF (for t
en
,t
dis
)
Transition is measured ± 500mV from steady
state voltage. (for t
en
,t
dis
)
DQ
C
L
including
scope and JIG
1TTL
Fig.1 Output load
(2) READ CYCLE
Limits
Symbol
t
CR
t
a(A)
t
a(S1)
t
a(S2)
t
a(OE)
t
dis(S1)
t
dis(S2)
t
dis(OE)
t
en(S1)
t
en(S2)
t
en(OE)
t
V(A)
Parameter
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S
1
high
Output disable time after S
2
low
Output disable time after OE high
Output enable time after S
1
low
Output enable time after S
2
high
Output enable time after OE low
Data valid time after address
-70H
Min
Max
70
70
70
70
35
25
25
25
10
10
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Symbol
t
CW
t
w(W)
t
su(A)
t
su(A-WH)
t
su(S1)
t
su(S2)
t
su(D)
t
h(D)
t
rec(W)
t
dis(W)
t
dis(OE)
t
en(W)
t
en(OE)
Parameter
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
Limits
-70H
Min
Max
70
55
0
65
65
65
30
0
0
25
25
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4