7th.July.2000 Ver. 1.1
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V108D series are determined by
a combination of the device control inputs S
1
,S
2
,W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level S
1
and the high level S
2
. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S
1
or
S
2
,whichever occurs first,requiring the set-up and hold time relative
to these edge to be maintained. The output enable input OE
directly controls the output stage. Setting the OE at a high level,
the output stage is in a high-impedance state, and the data bus
contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S
1
and S
2
are in an active state(S
1
=L,S
2
=H).
When setting S
1
at a high level or S
2
at a low level, the chip are in
a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S
1
and S
2
. The power supply current is reduced as low as the
stand-by current which is specified as I
CC3
or I
CC4
, and the memory
data can be held at +2V power supply, enabling battery back-up
operation during power failure or power-down operation in the non-
selected mode.
FUNCTION TABLE
S
1
X
H
L
L
L
S
2
L
X
H
H
H
W
X
X
L
H
H
Mode
DQ
OE
X Non selection High-impedance
X Non selection High-impedance
Din
X
Write
Dout
L
Read
High-impedance
H
I
CC
Stand-by
Stand-by
Active
Active
Active
Note 1: "H" and "L" in this table mean VIH and VIL, respectively.
2: "X" in this table should be "H" or "L".
BLOCK DIAGRAM
*
A3 9
A2 10
A5 7
A6 6
A7 5
A12 4
A14 3
A16 2
A15 31
17
18
15
14
13
12
11
10
7
*
21
22
13 DQ1
14 DQ2
15 DQ3
17 DQ4
18 DQ5
19 DQ6
20 DQ7
21 DQ8
DATA
INPUTS/
OUTPUTS
131072 WORDS
X 8 BITS
( 512 ROWS
X128 COLUMNS
X 16BLOCKS )
23
25
26
27
28
29
ADDRESS
INPUTS
A13 28
A8 27
A9 26
A11 25
4
3
2
1
5
A4 8
A1 11
A0 12
A10 23
16
19
20
31
32
8
24
30
6
WRITE
29 W CONTROL
INPUT
22 S1
30 S2
CHIP
SELECT
INPUTS
CLOCK
GENERATOR
OUTPUT
24 OE ENABLE
INPUT
32 V
CC
16 GND
(0V)
* Pin numbers inside dotted line show those of TSOP
2
RENESAS [ RENESAS TECHNOLOGY CORP ]
