MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus timing data formulas
Memory expansion and Microprocessor mode : Low-speed running (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) ≤ 25 MHz when
the clock source select bit = “0” , unless otherwise noted)
Symbol
Parameter
Data setup time with address stabilized
Data setup time with chip select stabilized
φ high-level pulse width, f low-level pulse width
2-φ access
3 × 109
3-φ access
5 × 109
4-φ access
7 × 109
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(A–DL/DH)
tsu(CS–DL/DH)
tw(φH), tw(φL)
– 60
– 60
– 60
f(XIN)
f(XIN)
f(XIN)
3 × 109
f(XIN)
1 × 109
f(XIN)
2 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
3 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
5 × 109
f(XIN)
7 × 109
f(XIN)
– 60
– 20
– 20
– 25
– 25
– 32
– 25
– 25
– 32
– 25
– 25
– 32
– 18
– 30
– 30
– 30
– 30
– 30
– 30
– 25
– 10
– 65
– 28
– 28
– 35
– 60
– 60
___
___
4 × 109
f(XIN)
__
__
tw(WR), tw(RD) WR, RD low-level pulse width
– 20
3 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
td(A–WR)
Address output delay time
Address output delay time
Address output delay time
– 25
– 25
– 65
– 25
– 25
– 65
– 25
– 25
– 65
– 18
td(A–RD)
td(A–ALE)
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
td(CS–WR)
td(CS–RD)
td(CS–ALE)
tw(ALE)
____
BHE output delay time
____
BHE outupt delay time
____
BHE output delay time
Chip select output delay time
Chip select output delay time
Chip select output delay time
ALE pulse width
3 × 109
f(XIN)
2 × 109
f(XIN)
th(WR–A)
Address hold time
th(RD–A)
Address hold time
____
td(WR–BHE)
td(RD–BHE)
td(WR–CS)
td(RD–CS)
BHE hold time
____
BHE hold time
Chip select hold time
Chip select holt time
t
h(WR–DLQ/DHQ)
Data hold time
t
pxz(WR–DLZ/DHZ)
Floating start delay time
Data setup time with address stabilized
Address output delay time
Address output delay time
Address output delay time
7 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
2 × 109
f(XIN)
5 × 109
f(XIN)
– 65
– 28
– 28
– 28
– 15
tsu(LA–DL)
td(LA–WR)
td(LA–RD)
– 65
1 × 109
f(XIN)
td(LA–ALE)
th(ALE–LA)
tpzx(RD–DLZ)
1 × 109
f(XIN)
ns
ns
Address hold time
1 × 109
f(XIN)
Floating release delay time
– 22
✽: f(XIN) ≤ 12.5 MHz when the clock source select bit = “1”
Note: When the clock source select bit is “1”, regard f(XIN) in tables as 2·f(XIN).
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RENESAS [ RENESAS TECHNOLOGY CORP ]
