MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PROCESSOR MODE
• BYTE pin
Bits 0 and 1 of processor mode register 0 (address 5E16) shown in
Figure 84 are used to select any mode of the single-chip mode, the
memory expansion mode and the microprocessor mode.
Ports P0 to P3, P10, P11 and a part of port P4 are used as I/O pins
of address, data, and control signals in the modes except the single-
chip mode.
When accessing the external memory, the level of the BYTE pin is
used to determine whether to use the data bus as 8-bit width or 16-
bit width.
The data bus has a width of 16 bits when the level of the BYTE pin is
“L”, and ports P10 and P11 become the data I/O pins.
The data bus has a width of 8 bits when level of the BYTE pin is “H”,
and port P10 becomes data I/O pins. Port P11 functions then as an
input/output port similarly in the single-chip mode.
Figure 85 shows the functions of ports P0 to P4, P10 and P11 in
each mode.
The external memory area depends on the mode. Figure 86 shows
the memory map for each mode. Refer to Figure 1 for the addresses
of RAM and ROM in the single-chip mode. The external memory
area can be accessed in the modes except the single-chip mode.
The access to the external memory is affected by the BYTE pin
When accessing the internal memory, the data bus always has a
width of 16 bits regardless of the BYTE pin level.
Address
7
6
0
5
4
3
2
1
0
Processor mode register 0 5E16
Processor mode bits
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Do not select.
Internal memory access bus cycle select bit (Note)
; Internal memory access condition in high-speed running
0 : 2-φ access for internal RAM; 3-φ access for internal ROM and SFR
1 : 2-φ access for internal RAM, internal ROM and SFR
Software reset bit
Reset occurs when writing “1” to this bit
Interrupt priority detection time select bit
0 0 : Select case 0 shown in Figure 13
0 1 : Select case 1 shown in Figure 13
1 0 : Select case 2 shown in Figure 13
Test mode bit
This bit must be fixed to “0.”
Clock φ1 output select bit
0 : No φ1 output
1 : φ1 output
Note : Clear bit 2 to “0” in low-speed running.
Fig. 84 Processor mode register 0 bit configuration
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RENESAS [ RENESAS TECHNOLOGY CORP ]
