MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
OUTPUT FUNCTION OF CHIP SELECT SIGNAL
___
___
Ports P90 to P94 can output the chip select signals CS0 to CS4 ac-
cording to the contents of chip select control register and chip select
area register. Bits 0 to 3 of chip select control register select either
chip select output (or addresses A20 to A22 output) or port function.
Additionally, bits 0 to 2 of chip select area register select the area in-
tended for each chip select signal.
7
6
5
4
3
2
1
0
Address
Chip select control register 6216
CS
CS
CS
CS
0
function select bit (Note 1)
: Port P9 function
: CS output
0
1
0
0
1
, CS2 function select bit (Note 2)
: Port P9 , P9 function
: CS1, CS output or A20, A21 output
0
1
1
2
2
Figure 87 shows the bit configuration of chip select control register
and Figure 88 shows that of chip select area register. Figure 89
shows the chip select areas.
3
function select bit (Note 2)
: Port P9 function
: CS output or A22 output
0
1
3
3
___
___
The bus cycle of CS3 and CS4 can be selected with bits 4 to 7 of chip
select control register. That selection is valid regardless of the bus
cycle select bits of processor mode register 1. Additionally, that bus
4
function select bit
: Port P9 function
: CS output
0
1
4
4
___
___
CS
3
bus cycle select bits
cycle selection of CS3 and CS4 is valid when selecting port function
___ ___
b5 b4 In high-speed In low-speed
with the CS3 and CS4 function select bits.
0
0
1
1
0
1
0
1
: 5-φ access
: 4-φ access
: 3-φ access
Do not select.
4-φ access
3-φ access
When accessing addresses in which the chip select area specified
by bits 0 to 2 of chip select area register and the internal memory
area overlap one another, chip select signals are not output. In this
case, its bus cycle is the cycle of internal memory area access.
It is possible to make the chip select output floating during Hold
state. That is realized by clearing the corresponding bit of port P9
direction register (address 1516) to “0” and bits 0 to 2 of waveform
output mode register (address 1A16) to “000”. The timing of Hold
start and termination is the same as that of addresses A0 to A19. (Re-
fer to section on processor mode.)
: Do not select. 2-φ access
CS
4
bus cycle select bits
b7 b6 In high-speed In low-speed
0
0
1
1
0
1
0
1
: 5-φ access
: 4-φ access
: 3-φ access
Do not select.
4-φ access
3-φ access
: Do not select. 2-φ access
Notes 1 : At reset, bit 0 becomes “0” when the CNVss pin’s level is “L”;
bit 0 becomes “1” when the CNVss pin’s level is “H”.
2 : Bits 6 and 7 of chip select area register (address 6316) specify
whether the chip select signal or address is output.
ADDRESS OUTPUT FUNCTION
Fig. 87 Chip select control register bit configuration
Port P91 to P93 can output the high-order addresses (A20 to A22) ac-
cording to bits 1 and 2 of chip select control register, and bits 6 and 7
of chip select area register.
___
___
___
About signal pairs of A20 and CS1, A21 and CS2, and A22 and CS3,
___
only one signal can be output. It is because chip select signals CS1
___
to CS3 output are common to ports P91 to P93 and addresses A20 to
A22 output.
It is possible to make the address output floating during Hold state.
That is realized by clearing the corresponding bit of port P9 direction
register (address 1516) to “0” and bits 0 to 2 of waveform output
mode register (address 1A16) to “000”. The timing of Hold start and
termination is the same as that of addressesA0 to A19. (Refer to sec-
tion on processor mode.)
75
RENESAS [ RENESAS TECHNOLOGY CORP ]
