MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus cycle in WIT/STP
direction register and port latch in WIT/STP state like ports in single-
When the WIT/STP instruction is executed with the standby state se-
lect bit 1 (bit 6 of particular function select register 0) = “0”, the clock
sources φ BIU and φ CPU or oscillation stop without waiting for
completion of the bus cycle being executed. Accordingly, the micro-
computer may enter WIT/STP state during bus access in which out-
chip mode. That is, when setting arbitrary data to the port latch and
the contents of direction register to “1”, that data is output from the
pin; when clearing the contents of direction register to “0”, the pin
becomes floating. This function makes the external bus arbitrary
state in WIT/STP state. When making pins floating, take consider-
ation with an external circuit to prevent their electric potential from
becoming half level of the electric potential.
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put of pins E, RD and WR is “L”.
Otherwise, when the WIT/STP instruction is executed with the
standby state select bit 1 = “1”, the clock sources φ BIU and φ CPU or
oscillation stop after completion of read or write in the bus access
cycle being executed. Consequently, in WIT/STP state, the bus be-
When writing to registers relevant to ports P0 to P3, P10, P11 in the
memory expansion/microprocessor mode, set the standby state se-
lect bit 0 to “1” before that write. If that bit is “0”, write is impossible,
because addresses corresponding to registers relevant to ports P0
to P3, P10, P11, which are addresses 216 to 916, 1616 to 1916, are
the external memory areas shown in Figure 86.
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comes the nonaccess state in which output of pins E, RD and WR is
“H”.
[Note]
Bus state in WIT/STP
Port P11 functions as an input/output port regardless of processor
modes when inputting “L” to the BYTE pin.
Normally, pins for the address output, data input/output and bus
control signal output in the memory expansion/microprocessor mode
(ports P0 to P3, P10, P11 in single-chip mode; refer to section on
Processor mode) retain the state as external bus pins when the
clock sources φ BIU and φ CPU stop in WIT/STP state.
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The RD pin state can arbitrarily be selected in WIT/STP state in the
memory expansion/microprocessor mode, too. Refer to the Table 8
for details.
However, when the WIT/STP instruction is executed with the
standby state select bit 0 (bit 5 of particular function select register
0) = “1”, those pins function depending on the contents of each port
Note that the function of arbitrary data output cannot be emulated
using a debugger.
Table 8 Signal output disable select bit function (bit 4 of particular function select register 1; Figure 62)
Function
Processor mode
Pin
Signal output disable select bit = “0”
Signal output disable select bit = “1”
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Outputs enable signal E.
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Outputs “L”.
Single-chip mode
E/RD
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Outputs RD/WR when accessing internal/
external memory area.
Outputs RD/WR when accessing external
memory area only.
RD, WR
Outputs “H” or “L” after executing WIT/STP
instruction
Outputs “H” or “L” after executing WIT/STP
instruction.
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RD
Outputs “H” when standby state select bit 1 is
“1”.
Outputs “L” when standby state select bit 0 is
“1”.
Memory expansion mode
Microprocessor mode
Outputs “H” when standby state select bit 1 is
“1” and standby state select bit 0 is “0.”
Outputs “L” when multiplex bus select bit =
“0”.
Outputs ALE.
ALE
Outputs ALE when multiplex bus select bit =
“1”.
Outputs clock φ 1 regardless of φ 1 output
select bit.
Outputs contents of port P42 latch; necessary
to set its direction register bit to “1”.
φ 1
Microprocessor mode
Note : All functions of signal output disable select bit cannot be debugged using an debugger.
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RENESAS [ RENESAS TECHNOLOGY CORP ]
