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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STACK POINTER (S)
Stack pointer (S) is a 16-bit register. It is used during a subroutine call
or interrupts. It is also used during stack, stack pointer relative, or
stack pointer relative indirect indexed Y addressing mode.
PROCESSOR STATUS REGISTER (PS)
Processor status register (PS) is an 11-bit register. It consists of a
flag to indicate the result of operation and CPU interrupt levels.
Branch operations can be performed by testing the flags C, Z, V, and
N.
The details of each bit of the processor status register are described
below.
PROGRAM COUNTER (PC)
Program counter (PC) is a 16-bit counter that indicates the low-order
16 bits of the next program memory address to be executed. There
is a bus interface unit between the program memory and the CPU,
so that the program memory is accessed through bus interface unit.
This is described later.
1. Carry flag (C)
The carry flag contains the carry or borrow generated by the ALU af-
ter an arithmetic operation. This flag is also affected by shift and ro-
tate instructions. This flag can be set and reset directly with the SEC
and CLC instructions or with the SEP and CLP instructions.
PROGRAM BANK REGISTER (PG)
Program bank register is an 8-bit register that indicates the high-or-
der 8 bits of the next program memory address to be executed.
When a carry occurs by incrementing the contents of the program
counter, the contents of the program bank register (PG) is increased
by 1. Also, when a carry or borrow occurs after adding or subtracting
the offset value to or from the contents of the program counter (PC)
using the branch instruction, the contents of the program bank regis-
ter (PG) is increased or decreased by 1, so that programs can be
written without worrying about bank boundaries.
2. Zero flag (Z)
The zero flag is set if the result of an arithmetic operation or data
transfer is zero and reset if it is not. This flag can be set and reset
directly with the SEP and CLP instructions.
3. Interrupt disable flag (I)
When the interrupt disable flag is set to “1”, all interrupts except
___
watchdog timer, DBC, and software interrupt are disabled. This flag
is set to “1” automatically when there is an interrupt. It can be set and
reset directly with the SEI and CLI instructions or SEP and CLP in-
structions.
DATA BANK REGISTER (DT)
Data bank register (DT) is an 8-bit register. With some addressing
modes, the data bank register (DT) is used to specify a part of the
memory address. The contents of data bank register (DT) is used as
the high-order 8 bits of a 24-bit address. Addressing modes that use
the data bank register (DT) are direct indirect, direct indexed X indi-
rect, direct indirect indexed Y, absolute, absolute bit, absolute in-
dexed X, absolute indexed Y, absolute bit relative, and stack pointer
relative indirect indexed Y.
4. Decimal mode flag (D)
The decimal mode flag determines whether addition and subtraction
are performed as binary or decimal. Binary arithmetic is performed
when this flag is “0”. If it is “1”, decimal arithmetic is performed with
each word treated as 2- or 4- digit decimal. Arithmetic operation is
performed using four digits when the data length flag m is “0” and
with two digits when it is “1”. Decimal adjust is automatically per-
formed. (Decimal operation is possible only with the ADC and SBC
instructions.) This flag can be set and reset with the SEP and CLP
instructions.
DIRECT PAGE REGISTER (DPR)
Direct page register (DPR) is a 16-bit register. Its contents is used as
the base address of a 256-byte direct page area. The direct page
area is allocated in bank 0
16
, but when the contents of DPR is
FF01
16
or greater, the direct page area spans across bank 0
16
and
bank 1
16
. All direct addressing modes use the contents of the direct
page register (DPR) to generate the data address. If the low-order 8
bits of the direct page register (DPR) is “00
16
”, the number of cycles
required to generate an address is minimized.
Normally the low-order 8 bits of the direct page register (DPR) is set
to “00
16
”.
10
RENESAS [ RENESAS TECHNOLOGY CORP ]
