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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37754M8C-XXXGP contains the following devices on a single
chip: ROM, RAM, CPU, bus interface unit, timers, UART, A-D con-
verter, D-A converter, I/O ports, clock generating circuit and others.
Each of these devices is described below.
MEMORY
The memory map is shown in Figure 1. The address space is 16
Mbytes from addresses 0
16
to FFFFFF
16
. The address space is di-
vided into 64-Kbyte units called banks. The banks are numbered
from 0
16
to FF
16
.
Internal ROM, internal RAM, and control registers for internal periph-
eral devices are assigned to bank 0
16
.
The 60-Kbyte area from addresses 1000
16
to FFFF
16
is the internal
ROM.
Addresses FFD2
16
to FFFF
16
are the RESET and interrupt vector
addresses and contain the interrupt vectors. Refer to the section on
interrupts for details.
The 2048-byte area from addresses 80
16
to 87F
16
contains the inter-
nal RAM. In addition to storing data, the RAM is used as stack during
a subroutine call, or interrupts.
Assigned to addresses 0
16
to 7F
16
are peripheral devices such as
I/O ports, A-D converter, D-A converter, UART, timer, and interrupt
control registers.
Additionally the internal ROM area can be modified by software.
Refer to the section on ROM area modification function for details.
A 256-byte direct page area can be allocated anywhere in bank 0
16
using the direct page register DPR. In direct page addressing mode,
the memory in the direct page area can be accessed with two words
thus reducing program steps.
Bank 0
16
Bank 1
16
FE0000
16
Bank FE
16
FEFFFF
16
FF0000
16
Bank FF
16
FFFFFF
16
•
•
•
•
•
•
•
•
•
•
•
•
•
000000
16
000000
16
00007F
16
000080
16
Internal RAM
2048 bytes
000000
16
Peripherai devices
control registers
see Fig. 2 for
further information
00007F
16
00FFFF
16
010000
16
00087F
16
Interrupt vector table
00FFD2
16
001000
16
INT
4
INT
3
A–D
01FFFF
16
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Internal ROM
60 Kbytes
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
INT
1
INT
0
Watchdog timer
DBC
BRK instruction
Zero divide
00FFFF
16
00FFFE
16
RESET
Note:
Internal ROM area can be modified. (Refer to the section on ROM area modification function.)
Fig. 1 Memory map
7
RENESAS [ RENESAS TECHNOLOGY CORP ]
