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M37754S4CGP 参数 Datasheet PDF下载

M37754S4CGP图片预览
型号: M37754S4CGP
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片16位CMOS微机 [SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER]
分类和应用: 微控制器和处理器外围集成电路计算机时钟
文件页数/大小: 115 页 / 1558 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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MITSUBISHI MICROCOMPUTERS  
M37754M8C-XXXGP, M37754M8C-XXXHP  
M37754S4CGP, M37754S4CHP  
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER  
Addresses FFD216 to FFFF16 are the RESET and interrupt vector  
addresses and contain the interrupt vectors. Refer to the section on  
BASIC FUNCTION BLOCKS  
The M37754M8C-XXXGP contains the following devices on a single  
chip: ROM, RAM, CPU, bus interface unit, timers, UART, A-D con-  
verter, D-A converter, I/O ports, clock generating circuit and others.  
Each of these devices is described below.  
interrupts for details.  
The 2048-byte area from addresses 8016 to 87F16 contains the inter-  
nal RAM. In addition to storing data, the RAM is used as stack during  
a subroutine call, or interrupts.  
Assigned to addresses 016 to 7F16 are peripheral devices such as  
I/O ports, A-D converter, D-A converter, UART, timer, and interrupt  
control registers.  
MEMORY  
The memory map is shown in Figure 1. The address space is 16  
Mbytes from addresses 016 to FFFFFF16. The address space is di-  
vided into 64-Kbyte units called banks. The banks are numbered  
from 016 to FF16.  
Additionally the internal ROM area can be modified by software.  
Refer to the section on ROM area modification function for details.  
A 256-byte direct page area can be allocated anywhere in bank 016  
using the direct page register DPR. In direct page addressing mode,  
the memory in the direct page area can be accessed with two words  
thus reducing program steps.  
Internal ROM, internal RAM, and control registers for internal periph-  
eral devices are assigned to bank 016.  
The 60-Kbyte area from addresses 100016 to FFFF16 is the internal  
ROM.  
00000016  
00000016  
00007F16  
00008016  
0000016  
Peripherai devices  
control registers  
Bank 016  
see Fig. 2 for  
further information  
Intern
20
00007F16  
00FFFF16  
01000016  
00087F16  
Interrupt vector table  
00FFD216  
INT4  
Bank 116  
INT3  
A–D  
01FFFF16  
UART1 transmit  
UART1 receive  
UART0 transmit  
UART0 receive  
Timer B2  
Timer B1  
Timer B0  
Internal ROM  
60 Kbytes  
Timer A4  
Timer A3  
Timer A2  
Timer A1  
Timer A0  
FE000016  
Bank FE16  
INT2  
INT1  
FEFFFF16  
FF000016  
INT0  
Watchdog timer  
DBC  
BRK instruction  
Zero divide  
Bank FF16  
00FFFE16  
RESET  
00FFFF16  
FFFFFF16  
Note: Internal ROM area can be modified. (Refer to the section on ROM area modification function.)  
Fig. 1 Memory map  
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