MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Instruction code read, data read, and data write are described below.
BUS CYCLE
The M37754M8C-XXXGP can select bus cycles shown in Figures 6
Instruction code read will be described first.
The CPU obtains instruction codes from the instruction queue buffer
and executes them. The CPU notifies the bus interface unit that CPU
is requesting an instruction code during an instruction code request
cycle. If the requested instruction code is not yet stored in the instruc-
tion queue buffer, the bus interface unit halts the CPU until it can
store more instructions than requested in the instruction queue
buffer.
and 7.
Central processing unit (CPU) running speed can be selected from
low-speed running (clock φ1 ≤ 12.5 MHz) and high-speed running
(clock φ1 ≤ 20 MHz); it is selected by bit 3 of processor mode register
1 (see Figure 9).
When accessing the external memory, the bus cycle is selected by
bits 4 and 5 of processor mode register 1.
Even if there is no instruction code request from the CPU, the bus
interface unit reads instruction codes from memory and stores them
in the instruction queue buffer when the instruction queue buffer is
empty or when only one instruction code is stored and the bus is idle
on the next cycle.
When accessing the internal memory, the bus cycle is selected by bit
2 of processor mode register 0 (see Figure 14).
Figure 8 shows output signals at 3-φ access in high-speed running.
The BHE signal becomes “L” when accessing the odd address.
Signals A0 and BHE indicate the differences between 1-byte read in
even address, 1-byte read in odd address, and simultaneous 2-byte
read in even and odd address; these signals also indicate the
differrences between 1-byte write in even address, 1-byte write in
odd address, and simultaneous 2-byte write in even and odd ad-
dress.
This is referred to as instruction pre-fetching.
Normally, when reading an instruction code from memory, if the ac-
cessed address is even, the next odd address is read together with
the instruction code and stored in the instruction queue buffer.
However, in memory expansion mode or microprocessor mode, if the
bus width select input (BYTE) is “H” and external data bus width is 8
bits, and if the address to be read is in external memory area or is
odd, only one byte is read and stored in the instruction queue buffer.
Data read and write are described below.
The A0 signal, which is bit 0 of address, becomes “L” when access-
ing an even address.
Table 1. Signals A0 and BHE
Access method
Signal
Simultaneous
access of 2 bytes in even address
Access of 1 byte Access of 1 byte
The CPU notifies the bus interface unit when performing data read
or write. At this time, the bus interface unit halts the CPU if the bus
interface unit is already using the bus or if there is a request with
higher priority. When data read or write is enabled, the bus interface
unit performs data read or write.
in odd address
A0
“L”
“L”
“L”
“H”
“L”
BHE
“H”
During data read, the CPU waits until the entire data is stored in the
data buffer. The bus interface unit sends the address sent from the
___
CPU to the address bus. Then it reads the memory when the RD sig-
nal is “L” and stores the result in the data buffer.
During data write, the CPU writes the data in the data buffer and the
bus interface unit writes it to memory. Therefore, the CPU can pro-
ceed to the next step without waiting for write to complete. The bus
interface unit sends the address sent from the CPU to the address
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bus. Then, when the WR signal is “L”, the bus interface unit sends
the data in the data buffer to the data bus and writes it to memory.
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RENESAS [ RENESAS TECHNOLOGY CORP ]
