MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
2
Table 7. Multi-master I C-BUS Interface Functions
MULTI-MASTER I C-BUS INTERFACE
2
The multi-master I C-BUS interface is a serial communications cir-
Function
Item
2
cuit, conforming to the Philips I C-BUS data transfer format. This
2
In conformity with Philips I C-BUS
standard:
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
Format
2
Figure 50 shows a block diagram of the multi-master I C-BUS inter-
2
face and Table 7 shows multi-master I C-BUS interface functions.
2
2
This multi-master I C-BUS interface consists of the I C address reg-
2
In conformity with Philips I C-BUS
2
2
2
ister, the I C data shift register, the I C clock control register, the I C
standard:
2
control register, the I C status register and other control circuits.
Master transmission
Master reception
Slave transmission
Slave reception
Communication mode
16.1 kHz to 400 kHz (at φ = 4 MHz)
SCL clock frequency
φ : System clock = f(XIN)/2
Note: We are not responsible for any third party’s infringement of
patent rights or other rights attributable to the use of the con-
2
trol function (bits 6 and 7 of the I C control register at address
2
00F916) for connections between the I C-BUS interface and
ports (SCL1, SCL2, SDA1, SDA2).
I2C address register (S0D)
b7
b0
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1SAD0 RBW
Address comparator
Serial
data
(SDA)
Noise
elimination
circuit
Data
control
circuit
b7
b0
I2C data shift register
b7
MST TRX BB PIN
b0
S0
AL AAS AD0 LRB
I2C status
AL
register (S1)
circuit
Internal data bus
BB
circuit
Serial
Noise
elimination
circuit
Clock
control
circuit
b7
b0
b7
b0
clock
(SCL)
FAST
MODE
ACK
BIT
10BIT
SAD
BSEL1 BSEL0
ALS
ACK
CCR4 CCR3 CCR2 CCR1 CCR0
ESO BC2 BC1 BC0
I2C clock control register (S1D)
System clock ( )
I2C clock control register (S2)
Clock division
Bit counter
2
Fig. 50. Block Diagram of Multi-master I C-BUS Interface
52
RENESAS [ RENESAS TECHNOLOGY CORP ]
