MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(12) Synchronous Signal Counter
The synchronous signal counter counts the composite sync signal
taken out from a video signal in the data slicer circuit or the vertical
synchronous signal Vsep as a count source.
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The count value in a certain time (T time) generated by f(XIN)/2 or
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f(XIN)/2 is stored into the 5-bit latch. Accordingly, the latch value
changes in the cycle of T time. When the count value exceeds “1F16,”
“1F16” is stored into the latch.
The latch value can be obtained by reading out the sync pulse counter
register (address 020F16). A count source is selected by bit 5 of the
sync pulse counter register.
The synchronous signal counter is used when bit 0 of PWM mode
register 1 (address 02EA16).
Figure 48 shows the structure of the sync pulse counter and Figure
49 shows the synchronous signal counter block diagram.
Sync Pulse Counter Register
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (SYC) [Address 020F16
]
R
R
W
—
B
Name
Count value
Functions
After reset
0
0
to
4
(SYC0 to SYC4)
5
Count source (SYC5)
0: HSYNC signal
1: Composite sync signal
0
0
R
R
W
—
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
6, 7
Fig. 48. Sync Pulse Counter Register
f(XIN)/213
Composite
sync signal
Reset
Counter
5-bit counter
H
SYNC signal
Sync pulse
counter register
Latch (5 bits)
b5
Selection gate : connected to black
colored side when
reset.
Data bus
Fig. 49. Synchronous Signal Counter Block Diagram
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RENESAS [ RENESAS TECHNOLOGY CORP ]
