MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
Figure 42 shows the structure of clock run-in detect register 2.
The contents of bits 2 to 0 of clock run-in detect register 2 and bit
1 of clock run-in register 2 are written at a falling of the horizontal
synchronous signal. For this reason, even if an instruction for setting
is executed, the contents of the register cannot be rewritten until a
falling of the horizontal synchronous signal.
After a falling of the clock run-in pulse set in bits 2 to 0 of clock run-
in detect register 2 (address 00E916) is detected, a start bit is
detected by sampling a comparator output. A sampling clock for
sampling is obtained by dividing the reference clock generated in
the timing signal generating circuit by 13.
Clock Run-in Register 2
b7 b6 b5 b4 b3 b2 b1 b0
1
0
0
1
1
1
1
Clock run-in register 2 (CR2) [Address 00E716
]
R
R
W
W
B
Name
Functions
After reset
0
0,
Fix these bits to “1.”
2 to 4,
7
0
0
R
R
W
W
1
Start bit detecting
method selection bit
(CR21)
0: Method 1
1: Method 2
5, 6
Fix these bits to “0.”
Fig. 41. Clock Run-in Register 2
Clock Run-in Detect Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register 2 (CRD2) [Address 00E916
]
R
W
W
B
Name
Functions
After reset
0
to
2
0
R
Clock run-in pulses for
sampling
(CRD20 to CRD22)
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : Not available
1 : 1st pulse
0 : 2nd pulse
1 : 3rd pulse
0 : 4th pulse
1 : 5th pulse
0 : 6th pulse
1 : 7th pulse
Time from detection of a start
bit to occurrence of a data clock
= (13 + set value) ✕
3
to
7
0
R
W
Data clock generating
time
(CRD23 to CRD27)
reference clock period
Fig. 42. Clock Run-in Detect Register 2
46
RENESAS [ RENESAS TECHNOLOGY CORP ]
